Invention Grant
US09524986B2 Trapping dislocations in high-mobility fins below isolation layer
有权
在隔离层下方的高迁移率翅片中捕获位错
- Patent Title: Trapping dislocations in high-mobility fins below isolation layer
- Patent Title (中): 在隔离层下方的高迁移率翅片中捕获位错
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Application No.: US14315362Application Date: 2014-06-26
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Publication No.: US09524986B2Publication Date: 2016-12-20
- Inventor: Michael P. Chudzik , Ramachandra Divakaruni , Judson R. Holt , Arvind Kumar , Unoh Kwon
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Scully Scott Murphy and Presser
- Agent Frank Digiglio
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L27/12 ; H01L29/78 ; H01L29/66 ; H01L21/84 ; H01L21/306 ; H01L21/311 ; H01L29/16 ; H01L21/3105

Abstract:
The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a high-mobility fin field effect transistor (finFET) fin in a silicon semiconductor on insulator (SOI) substrate by trapping crystalline lattice dislocations that occur during epitaxial growth in a recess formed in a semiconductor layer. The crystalline lattice dislocations may remain trapped below a thin isolation layer, thereby reducing device thickness and the need for high-aspect ratio etching and fin formation.
Public/Granted literature
- US20150380438A1 TRAPPING DISLOCATIONS IN HIGH-MOBILITY FINS BELOW ISOLATION LAYER Public/Granted day:2015-12-31
Information query
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