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    Merged source drain epitaxy
    2.
    发明授权
    Merged source drain epitaxy 有权
    合并源漏外延

    公开(公告)号：US09437496B1

    公开(公告)日：2016-09-06

    申请号：US14727219

    申请日：2015-06-01

    申请人： GLOBALFOUNDRIES INC.

    发明人： Michael P. Chudzik ,  Brian J. Greene ,  Edward P. Maciejewski ,  Kevin McStay ,  Shreesh Narasimha ,  Chengwen Pei ,  Werner A. Rausch

    IPC分类号： H01L29/10 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/02

    CPC分类号： H01L29/66795 ,  H01L29/66545

    摘要： A semiconductor device such as a FinFET includes a plurality of fins formed upon a substrate and a gate covering a portion of the fins. Diamond-shaped volumes are formed on the sidewalls of the fins by epitaxial growth which may be limited to avoid merging of the volumes or where the epitaxy volumes have merged. Because of the difficulties in managing merging of the diamond-shaped volumes, a controlled merger of the diamond-shaped volumes includes depositing an amorphous semiconductor material upon the diamond-shaped volumes and a crystallization process to crystallize the deposited semiconductor material on the diamond-shaped volumes to fabricate controllable and uniformly merged source drain.

    摘要翻译： 诸如FinFET的半导体器件包括形成在衬底上的多个鳍片和覆盖鳍片的一部分的栅极。 通过外延生长在翅片的侧壁上形成菱形体积，其可以被限制以避免体积的合并或外延体积合并的位置。 由于难以管理菱形体积的合并，钻石形容积的受控合并包括在金刚石体积上沉积非晶半导体材料和结晶过程以将沉积的半导体材料结晶在菱形体上 体积来制造可控和均匀合并的源极漏极。

    Variable length multi-channel replacement metal gate including silicon hard mask
    3.
    发明授权
    Variable length multi-channel replacement metal gate including silicon hard mask 有权
    可变长度多通道替代金属栅极，包括硅硬掩模

    公开(公告)号：US09397177B2

    公开(公告)日：2016-07-19

    申请号：US14088462

    申请日：2013-11-25

    申请人： GLOBALFOUNDRIES INC.

    发明人： Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon

    IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L21/321

    CPC分类号： H01L29/42376 ,  H01L21/28088 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/823807 ,  H01L21/82385 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

    摘要： A method of forming a semiconductor device includes forming first and second semiconductor structures on a semiconductor substrate. The first semiconductor structure includes a first gate channel region having a first gate length, and the second semiconductor structure including a second gate channel region having a second gate length that is greater than the first gate length. The method further includes depositing a work function metal layer in each of a first gate void formed at the first gate channel region and a second gate void formed at the second gate channel region. The method further includes depositing a semiconductor masking layer on the work function metal layer, and simultaneously etching the silicon masking layer located at the first and second gate channel regions to re-expose the first and second gate voids. A low-resistive metal is deposited in the first and second gate voids to form low-resistive metal gate stacks.

    摘要翻译： 形成半导体器件的方法包括在半导体衬底上形成第一和第二半导体结构。 第一半导体结构包括具有第一栅极长度的第一栅极沟道区，并且第二半导体结构包括具有大于第一栅极长度的第二栅极长度的第二栅极沟道区。 该方法还包括在第一栅极沟道区域中形成的第一栅极空隙和形成在第二栅极沟道区域处的第二栅极空穴中沉积功函数金属层。 该方法还包括在功函数金属层上沉积半导体掩模层，同时蚀刻位于第一和第二栅极沟道区的硅掩模层，以重新暴露第一和第二栅极空隙。 在第一和第二栅极空隙中沉积低电阻金属以形成低电阻金属栅极叠层。

    Concurrently Forming nFET and pFET Gate Dielectric Layers
    6.
    发明申请
    Concurrently Forming nFET and pFET Gate Dielectric Layers 有权
    并联形成nFET和pFET栅介质层

    公开(公告)号：US20140187028A1

    公开(公告)日：2014-07-03

    申请号：US13732455

    申请日：2013-01-02

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

    发明人： Takashi Ando ,  Maryjane Brodsky ,  Michael P. Chudzik ,  Min Dai ,  Siddarth A. Krishnan ,  Joseph F. Shepard, JR. ,  Yanfeng Wang ,  Jinping Liu

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823857

    摘要： Embodiments include methods of forming an nFET-tuned gate dielectric and a pFET-tuned gate dielectric. Methods may include forming a high-k layer above a substrate having a pFET region and an nFET region, forming a first sacrificial layer, a pFET work-function metal layer, and a second sacrificial layer above the first high-k layer in the pFET region, and an nFET work-function metal layer above the first high-k layer in the nFET region and above the second sacrificial layer in the pFET region. The first high-k layer then may be annealed to form an nFET gate dielectric layer in the nFET region and a pFET gate dielectric layer in the pFET region. The first high-k layer may be annealed in the presence of a nitrogen source to cause atoms from the nitrogen source to diffuse into the first high-k layer in the nFET region.

    摘要翻译： 实施例包括形成nFET调谐的栅极电介质和pFET调谐的栅极电介质的方法。 方法可以包括在pFET区域和nFET区域上形成高k层，形成第一牺牲层，pFET功函数金属层和在pFET中的第一高k层上方的第二牺牲层 区域，以及在nFET区域中的第一高k层上方的nFET功函数金属层，并且在pFET区域中的第二牺牲层上方。 第一高k层然后可以退火以在nFET区域中形成nFET栅极介电层，并在pFET区域中形成pFET栅极电介质层。 第一高k层可以在存在氮源的情况下进行退火，以使来自氮源的原子扩散到nFET区域中的第一高k层。

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING REPLACEMENT METAL GATE PROCESS INCORPORATING A CONDUCTIVE DUMMY GATE LAYER
    10.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING REPLACEMENT METAL GATE PROCESS INCORPORATING A CONDUCTIVE DUMMY GATE LAYER 有权
    制造半导体器件的方法，包括更换金属栅极工艺，包括导电的DUMMY GATE层

    公开(公告)号：US20140120708A1

    公开(公告)日：2014-05-01

    申请号：US13664744

    申请日：2012-10-31

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

    发明人： Michael P. Chudzik ,  Min Dai ,  Xiang Hu ,  Jinping Liu ,  Yanxiang Liu ,  Xiaodong Yang

    IPC分类号： H01L21/28

    CPC分类号： H01L29/66545 ,  H01L21/2807 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/823462

    摘要： A method of manufacturing a semiconductor device including a replacement metal gate process incorporating a conductive dummy gate layer (e.g., silicon germanium (SiGe), titanium nitride, etc.) and a related are disclosed. The method includes forming an oxide layer on a substrate; removing a gate portion of the oxide layer from the substrate in a first region of the semiconductor device; forming a conductive dummy gate layer on the semiconductor device in the first region; and forming a gate on the semiconductor device, the gate including a gate conductor disposed in the first region and directly connected to the substrate.

    摘要翻译： 公开了一种制造半导体器件的方法，该半导体器件包括结合导电虚拟栅极层（例如硅锗（SiGe），氮化钛等）的替代金属栅极工艺）和相关的方法。 该方法包括在衬底上形成氧化物层; 在所述半导体器件的第一区域中从所述衬底去除所述氧化物层的栅极部分; 在所述第一区域中的所述半导体器件上形成导电虚拟栅极层; 以及在所述半导体器件上形成栅极，所述栅极包括设置在所述第一区域中并直接连接到所述衬底的栅极导体。