Invention Grant
- Patent Title: Multistage memory cell read
- Patent Title (中): 多级存储单元读取
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Application No.: US14846898Application Date: 2015-09-07
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Publication No.: US09543005B2Publication Date: 2017-01-10
- Inventor: Sandeep K Guliani , Kiran Pangal , Balaji Srinivasan , Chaohong Hu
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law
- Main IPC: G11C13/00
- IPC: G11C13/00 ; G11C7/00 ; G11C13/02 ; G11C8/08 ; G11C16/26 ; G11C11/16 ; G11C8/14 ; G11C11/419 ; G11C11/56

Abstract:
A multistage read can dynamically change wordline capacitance as a function of threshold voltage of a memory cell being read. The multistage read can reduce current spikes and reduce the heating up of a memory cell during a read. A memory device includes a global wordline driver to connect a wordline of a selected memory cell to the sensing circuit, and a local wordline driver local to the memory cell. After the wordline is charged to a read voltage, control logic can selectively enable and disable a portion or all of the global wordline driver and the local wordline driver in conjunction with applying different discrete voltage levels to the bitline to perform a multistage read.
Public/Granted literature
- US20160217853A1 MULTISTAGE MEMORY CELL READ Public/Granted day:2016-07-28
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