Invention Grant
US09543044B2 System and method for improving memory performance and identifying weak bits
有权
用于提高记忆性能和识别弱位的系统和方法
- Patent Title: System and method for improving memory performance and identifying weak bits
- Patent Title (中): 用于提高记忆性能和识别弱位的系统和方法
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Application No.: US14074341Application Date: 2013-11-07
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Publication No.: US09543044B2Publication Date: 2017-01-10
- Inventor: Abhishek Jain , Andrea Mario Veggetti , Amit Chhabra
- Applicant: STMicroelectronics International N.V. , STMicroelectronics S.R.L.
- Applicant Address: NL Amsterdam IT Agrate Brianza (MB)
- Assignee: STMicroelectronics International N.V.,STMicroelectronics S.R.L.
- Current Assignee: STMicroelectronics International N.V.,STMicroelectronics S.R.L.
- Current Assignee Address: NL Amsterdam IT Agrate Brianza (MB)
- Agency: Slater Matsil, LLP
- Main IPC: G11C29/48
- IPC: G11C29/48 ; G06F1/08 ; G11C29/24 ; G11C29/52 ; G11C29/54

Abstract:
According to an embodiment described herein, a method for testing a memory includes receiving an address and a start signal at a memory, and generating a first detector pulse at a test circuit in response to the start signal. The first detector pulse has a leading edge and a trailing edge. A data transition of a bit associated with the address is detected. The bit is a functional bit. The method further includes determining whether the bit is a weak bit by determining whether the data transition occurred after the trailing edge.
Public/Granted literature
- US20150127998A1 System and Method for Improving Memory Performance and Identifying Weak Bits Public/Granted day:2015-05-07
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