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1.发明授权公开(公告)号：US09543044B2
公开(公告)日：2017-01-10
申请号：US14074341
申请日：2013-11-07
Inventor： Abhishek Jain , Andrea Mario Veggetti , Amit Chhabra
Abstract: According to an embodiment described herein, a method for testing a memory includes receiving an address and a start signal at a memory, and generating a first detector pulse at a test circuit in response to the start signal. The first detector pulse has a leading edge and a trailing edge. A data transition of a bit associated with the address is detected. The bit is a functional bit. The method further includes determining whether the bit is a weak bit by determining whether the data transition occurred after the trailing edge.
Abstract translation: 根据本文描述的实施例，用于测试存储器的方法包括在存储器处接收地址和起始信号，并且响应于起始信号在测试电路产生第一检测器脉冲。 第一检测器脉冲具有前沿和后沿。 检测与地址相关联的位的数据转换。 该位是一个功能位。 该方法还包括通过确定在后沿之后是否发生数据转换来确定该位是否为弱位。
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公开(公告)号：US09728232B2
公开(公告)日：2017-08-08
申请号：US15167101
申请日：2016-05-27
Applicant: STMicroelectronics International N.V.
Inventor： Amit Chhabra
CPC classification number: G11C5/148 , G05F1/46 , G05F1/465 , H03K3/0377 , H03K5/082 , H03K17/223
Abstract: When powering-up or exiting from a sleep mode, the ramping up of various supply voltage nodes may occur at different rates. Thus, in a dual-rail memory circuit, a first voltage rail may be at voltage before a second voltage rail. Such a transient state of operation may lead to current spikes that unnecessarily draw power and introduce undesired inefficiency. An internal sleep signal generation circuit in the dual-rail memory circuit precisely controls an internal sleep signal such that the transition from off or sleep mode to operating mode is set to assure that the supply voltage nodes are close enough to the at-voltage operating level before releasing the sleep mode.
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公开(公告)号：US09559665B2
公开(公告)日：2017-01-31
申请号：US14788714
申请日：2015-06-30
Applicant: STMicroelectronics International N.V.
Inventor： Amit Chhabra
IPC: H03K3/011 , G11C11/417 , H03K17/687 , H01L27/11
CPC classification number: H03K3/011 , G01K3/005 , G01K7/01 , G11C5/146 , G11C7/04 , G11C11/417 , H01L27/1104 , H03K17/687
Abstract: An integrated circuit die includes a plurality of transistors formed in a semiconductor substrate, the body regions of the transistors on a doped well region of the semiconductor substrate. A threshold detector selectively applies either a first voltage or second voltage to the doped well region based on whether the temperature of the semiconductor substrate is above or below a threshold temperature.
Abstract translation: 集成电路管芯包括形成在半导体衬底中的多个晶体管，在半导体衬底的掺杂阱区域上的晶体管的体区。 阈值检测器基于半导体衬底的温度是高于还是低于阈值温度来选择性地将第一电压或第二电压施加到掺杂阱区。
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公开(公告)号：US20160049189A1
公开(公告)日：2016-02-18
申请号：US14813278
申请日：2015-07-30
Inventor： Christophe Lecocq , Kaya Can Akyel , Amit Chhabra , Dibya Dipti
IPC: G11C11/417
CPC classification number: G11C11/417 , G11C11/412 , H01L27/1104
Abstract: An SRAM cell is formed of FDSOI-type NMOS and PMOS transistors. A doped well extends under the NMOS and PMOS transistors and is separated therefrom by an insulating layer. A bias voltage is applied to the doped well. The applied bias voltage is adjusted according to a state of the memory cell. For example, a temperature of the memory cell is sensed and the bias voltage adjusted as a function of the sensed temperature. The adjustment in the bias voltage is configured so that threshold voltages of the NMOS and PMOS transistors are substantially equal to n and p target threshold voltages, respectively.
Abstract translation: SRAM单元由FDSOI型NMOS和PMOS晶体管形成。 掺杂阱在NMOS和PMOS晶体管的下方延伸，并通过绝缘层与其分离。 偏置电压施加到掺杂阱。 施加的偏置电压根据存储单元的状态进行调整。 例如，感测存储器单元的温度，并根据检测到的温度调整偏置电压。 偏置电压的调整被配置为使得NMOS和PMOS晶体管的阈值电压分别基本上等于n和p个目标阈值电压。
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5.发明申请SYSTEM AND METHOD FOR AUTOMATIC DETECTION OF POWER UP FOR A DUAL-RAIL CIRCUIT 审中-公开用于双轨电路自动检测功率的系统和方法公开(公告)号：US20160275999A1
公开(公告)日：2016-09-22
申请号：US15167101
申请日：2016-05-27
Applicant: STMicroelectronics International N.V.
Inventor： Amit Chhabra
CPC classification number: G11C5/148 , G05F1/46 , G05F1/465 , H03K3/0377 , H03K5/082 , H03K17/223
Abstract: When powering-up or exiting from a sleep mode, the ramping up of various supply voltage nodes may occur at different rates. Thus, in a dual-rail memory circuit, a first voltage rail may be at voltage before a second voltage rail. Such a transient state of operation may lead to current spikes that unnecessarily draw power and introduce undesired inefficiency. An internal sleep signal generation circuit in the dual-rail memory circuit precisely controls an internal sleep signal such that the transition from off or sleep mode to operating mode is set to assure that the supply voltage nodes are close enough to the at-voltage operating level before releasing the sleep mode.
Abstract translation: 当从睡眠模式上电或退出时，各种电源节点的升高可能以不同的速率发生。 因此，在双轨存储器电路中，第一电压轨可以在第二电压轨之前处于电压。 这种瞬时的操作状态可能导致电流尖峰不必要地抽取功率并引入不期望的低效率。 双轨存储器电路中的内部睡眠信号产生电路精确地控制内部睡眠信号，使得从关闭或休眠模式向工作模式的转变被设置为确保电源电压节点足够接近于工作电压 在释放睡眠模式之前。
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Patent Agency Ranking
6.发明授权公开(公告)号：US09378779B2
公开(公告)日：2016-06-28
申请号：US14329747
申请日：2014-07-11
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Amit Chhabra
CPC classification number: G11C5/148 , G05F1/46 , G05F1/465 , H03K3/0377 , H03K5/082 , H03K17/223
Abstract: A dual-rail memory circuit having a sleep generation circuit configured to prevent undesired currents from being generated during power-up and while transitioning power states. When a dual-rail memory circuit is powering-up or exiting from a sleep mode, the ramping up of various supply voltage nodes may occur at different rates. Thus, in a dual-rail memory circuit, a first voltage rail may be at voltage before a second voltage rail. Such a transient state of operation may lead to current spikes that unnecessarily draw power and introduce undesired inefficiency. An internal sleep signal generation circuit in a dual-rail memory circuit may be used to precisely control an internal sleep signal such that the transition from off or sleep mode to operating mode is set to assure that the supply voltage nodes are close enough to the at-voltage operating level before releasing the sleep mode.
Abstract translation: 具有睡眠产生电路的双轨存储器电路，其被配置为防止在上电期间和在转换功率状态期间产生不期望的电流。 当双轨存储器电路上电或从睡眠模式退出时，各种电源节点的升高可以以不同的速率发生。 因此，在双轨存储器电路中，第一电压轨可以在第二电压轨之前处于电压。 这种瞬时的操作状态可能导致电流尖峰不必要地抽取功率并引入不期望的低效率。 双轨存储器电路中的内部睡眠信号产生电路可以用于精确地控制内部睡眠信号，使得从关闭或休眠模式到操作模式的转变被设置为确保电源电压节点足够接近于at - 释放睡眠模式前的电压工作电平。
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7.发明申请公开(公告)号：US20150127998A1
公开(公告)日：2015-05-07
申请号：US14074341
申请日：2013-11-07
Applicant: STMicroelectronics International N.V.
Inventor： Andrea Mario Veggetti , Abhishek Jain , Amit Chhabra
Abstract: According to an embodiment described herein, a method for testing a memory includes receiving an address and a start signal at a memory, and generating a first detector pulse at a test circuit in response to the start signal. The first detector pulse has a leading edge and a trailing edge. A data transition of a bit associated with the address is detected. The bit is a functional bit. The method further includes determining whether the bit is a weak bit by determining whether the data transition occurred after the trailing edge.
Abstract translation: 根据本文描述的实施例，用于测试存储器的方法包括在存储器处接收地址和起始信号，并且响应于起始信号在测试电路产生第一检测器脉冲。 第一检测器脉冲具有前沿和后沿。 检测与地址相关联的位的数据转换。 该位是一个功能位。 该方法还包括通过确定在后沿之后是否发生数据转换来确定该位是否为弱位。
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公开(公告)号：US09659933B2
公开(公告)日：2017-05-23
申请号：US14697461
申请日：2015-04-27
Applicant: STMicroelectronics International N.V.
Inventor： Vikas Rana , Amit Chhabra
IPC: H03K17/693 , H01L27/092 , H01L27/12 , H03K17/00
CPC classification number: H03K17/693 , H01L27/092 , H01L27/1203 , H03K17/005 , H03K2217/0018
Abstract: An integrated circuit die includes a plurality of transistors formed in a semiconductor substrate, the body regions of the transistors on a doped well region of the semiconductor substrate. A body bias voltage generator generates a positive body bias voltage, and a negative body bias voltage in the ground body bias voltage. A multiplexer selectively outputs one of the positive, negative, or ground body bias voltage to the doped well region of the semiconductor substrate based on the temperature of the semiconductor substrate.
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公开(公告)号：US20170005641A1
公开(公告)日：2017-01-05
申请号：US14788714
申请日：2015-06-30
Applicant: STMicroelectronics International N.V.
Inventor： Amit Chhabra
IPC: H03K3/011 , H03K17/687 , H01L27/11 , G11C11/417
CPC classification number: H03K3/011 , G01K3/005 , G01K7/01 , G11C5/146 , G11C7/04 , G11C11/417 , H01L27/1104 , H03K17/687
Abstract: An integrated circuit die includes a plurality of transistors formed in a semiconductor substrate, the body regions of the transistors on a doped well region of the semiconductor substrate. A threshold detector selectively applies either a first voltage or second voltage to the doped well region based on whether the temperature of the semiconductor substrate is above or below a threshold temperature.
Abstract translation: 集成电路管芯包括形成在半导体衬底中的多个晶体管，在半导体衬底的掺杂阱区域上的晶体管的体区。 基于半导体衬底的温度是高于还是低于阈值温度，阈值检测器选择性地将第一电压或第二电压施加到掺杂阱区。
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公开(公告)号：US09396790B1
公开(公告)日：2016-07-19
申请号：US14755362
申请日：2015-06-30
Applicant: STMicroelectronics International N.V.
Inventor： Amit Chhabra , Kailash Digari
IPC: G11C11/41 , G11C11/419
CPC classification number: G11C11/419 , G11C5/14 , G11C11/417
Abstract: A multi-supply dual port register file is disclosed. The register file may be used for transferring data between two power domains that operate on different voltages or frequencies. The register file comprises a memory cell that stores the data transferred between the domains. The memory cell may be independently supplied by a reference voltage independent of that of the memory periphery. A write power domain write data to the memory cell in accordance with its operating voltage and frequency and an independent read power domain may read data from the memory cell in accordance with its independent operating voltage and frequency. The register file facilitates efficient crossing between the read and write power domains.
Abstract translation: 公开了一种多电源双端口寄存器文件。 寄存器文件可用于在不同电压或频率下工作的两个电源域之间传输数据。 寄存器文件包括存储在域之间传送的数据的存储单元。 存储单元可以独立于存储器周边的参考电压独立地提供。 写功率域根据其工作电压和频率将数据写入存储单元，并且独立的读功率域可以根据其独立的工作电压和频率从存储单元读取数据。 寄存器文件有助于读写功率域之间的有效交叉。
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