Invention Grant
- Patent Title: Electrical connection for chip scale packaging
- Patent Title (中): 电子连接用于芯片级封装
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Application No.: US13269310Application Date: 2011-10-07
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Publication No.: US09548281B2Publication Date: 2017-01-17
- Inventor: Ming-Chih Yew , Wen-Yi Lin , Fu-Jen Li , Po-Yao Lin
- Applicant: Ming-Chih Yew , Wen-Yi Lin , Fu-Jen Li , Po-Yao Lin
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/28 ; H01L23/00 ; H01L23/488 ; H01L23/31 ; H01L23/525
Abstract:
A system and method for providing a post-passivation opening and undercontact metallization is provided. An embodiment comprises an opening through the post-passivation which has a first dimension longer than a second dimension, wherein the first dimension is aligned perpendicular to a chip's direction of coefficient of thermal expansion mismatch. By shaping and aligning the opening through the post-passivation layer in this fashion, the post-passivation layer helps to shield the underlying layers from stresses generated from mismatches of the materials' coefficient of thermal expansion.
Public/Granted literature
- US20130087892A1 Electrical Connection for Chip Scale Packaging Public/Granted day:2013-04-11
Information query
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