A power converter has a phase leg with upper and lower switching devices coupled across a DC link. A junction between the devices is coupled to a load. A current sensor detects direction of current flow from the junction to the load. A gate driver activates the devices according to upper and lower gate signals in response to pulse-width modulation (PWM) to generate nominal gate signals from a variable duty cycle. When the positive current direction is detected then the upper gate signal has turn-on and turn-off times shifted by a predetermined offset with respect to the nominal signals, and dead-times are added to the lower gate signals. When the negative direction is detected then the lower gate signal has turn-on and turn-off times shifted by the predetermined offset with respect to the nominal signals, and dead-times are added to the upper gate signals.