Invention Grant
- Patent Title: 1D-2R memory architecture
- Patent Title (中): 1D-2R内存架构
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Application No.: US14568011Application Date: 2014-12-11
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Publication No.: US09570165B2Publication Date: 2017-02-14
- Inventor: Deepak Chandra Sekar , Gary Bela Bronner , Christophe J. Chevallier , Lidia Vereen , Philip F. S. Swab , Elizabeth Friend , Mehmet Gunhan Ertosun
- Applicant: Rambus Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: Rambus Inc.
- Current Assignee: Rambus Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Lowenstein Sandler LLP
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C13/00 ; G11C11/56 ; H01L27/24 ; H01L45/00
Abstract:
A memory device includes an array of resistive memory cells. Each resistive memory cell in the array includes a first resistive memory element, a second resistive memory element, and a two-terminal switching element. The first resistive memory element is electrically coupled to the second resistive memory element and to the switching element at a common node.
Public/Granted literature
- US20150162382A1 1D-2R MEMORY ARCHITECTURE Public/Granted day:2015-06-11
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