Invention Grant
US09570200B2 Resistive memory device having memory cell arrays with multiple stack layers and bad-region managing circuit and method for managing short failure
有权
具有具有多个堆叠层的存储单元阵列和不良区域管理电路的电阻式存储器件以及用于管理短路故障的方法
- Patent Title: Resistive memory device having memory cell arrays with multiple stack layers and bad-region managing circuit and method for managing short failure
- Patent Title (中): 具有具有多个堆叠层的存储单元阵列和不良区域管理电路的电阻式存储器件以及用于管理短路故障的方法
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Application No.: US14743521Application Date: 2015-06-18
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Publication No.: US09570200B2Publication Date: 2017-02-14
- Inventor: Hyo-Jin Kwon , Dae-Seok Byeon , Yeong-Taek Lee , Chi-Weon Yoon , Yong-Kyu Lee , Hyun-Kook Park
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Volentine & Whitt, PLLC
- Priority: KR10-2014-0100660 20140805
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C29/00 ; G11C13/00 ; G11C11/16 ; G11C29/44
Abstract:
A resistive memory device includes a memory cell array that includes a plurality of memory layers stacked in a vertical direction. Each of the plurality of memory layers includes a plurality of memory cells disposed in regions where a plurality of first lines and a plurality of second lines cross each other. A bad region management unit defines as a bad region a first memory layer including a bad cell from among the plurality of memory cells and at least one second memory layer.
Public/Granted literature
- US20160042811A1 RESISTIVE MEMORY DEVICE AND OPERATING METHOD THEREOF Public/Granted day:2016-02-11
Information query
