-
公开(公告)号：US09437290B2
公开(公告)日：2016-09-06
申请号：US14631182
申请日：2015-02-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong-Kyu Lee , Dae-Seok Byeon , Hyo-Jin Kwon , Hyun-Kook Park , Chi-Weon Yoon , Yeong-Taek Lee
CPC classification number: G11C13/0033 , G11C11/5607 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007
Abstract: A method of operating a resistive memory device including a plurality of memory cells comprises determining whether to perform a refresh operation on memory cells in a memory cell array; determining a resistance state of each of at least some of the memory cells; and performing a re-writing operation on a first memory cell having a resistance state from among a plurality of resistance states that is equal to or less than a critical resistance level.
Abstract translation: 一种操作包括多个存储单元的电阻式存储器件的方法包括：确定是否对存储单元阵列中的存储器单元执行刷新操作; 确定所述至少一些所述存储器单元中的每一个的电阻状态; 以及在等于或小于临界电阻水平的多个电阻状态之中对具有电阻状态的第一存储单元执行重写操作。
-
公开(公告)号：US09659645B2
公开(公告)日：2017-05-23
申请号：US14665140
申请日：2015-03-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun-Kook Park , Yeong-Taek Lee , Dae-Seok Byeon , Yong-Kyu Lee , Hyo-Jin Kwon
CPC classification number: G11C13/0069 , G11C11/1675 , G11C11/1693 , G11C13/0002 , G11C13/0023 , G11C13/0061 , G11C13/0064 , G11C13/0097 , G11C2213/71
Abstract: A method of writing data in a resistive memory device having a memory cell array divided into first and second tiles includes; performing a first simultaneous write operation by performing a set write operation performed on resistive memory cells of the first tile while simultaneously performing a reset write operation on resistive memory cells of the second tile in response to the write command, and performing a second simultaneous write operation by performing a reset write operation on resistive memory cells of the first tile while simultaneously performing a set write operation on resistive memory cells of the second tile in response to the write command.
-
公开(公告)号：US09530494B2
公开(公告)日：2016-12-27
申请号：US14697244
申请日：2015-04-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong-Kyu Lee , Dae-Seok Byeon , Yeong-Taek Lee , Chi-Weon Yoon , Hyun-Kook Park , Hyo-Jin Kwon
CPC classification number: G11C13/0069 , G11C13/0033 , G11C13/0035 , G11C16/10 , G11C2013/0092
Abstract: A method of operating a memory device, which includes of memory cells respectively arranged in regions where first signal lines and second lines cross each other, includes determining a plurality of pulses so that each of the plurality of pulses that are sequentially applied to a selected memory cell among the plurality of memory cells is changed according to a number of times of executing programming loops. In response to the change of the plurality of pulses, at least one of a first inhibit voltage and a second inhibit voltage is determined so that a voltage level of at least one of the first and second inhibit voltages that are respectively applied to unselected first and second signal lines connected to unselected memory cells among the plurality of memory cells is changed according to the number of times of executing the programming loops.
Abstract translation: 一种操作存储器件的方法，所述存储器件包括分别布置在第一信号线和第二线彼此交叉的区域中的存储器单元，包括确定多个脉冲，使得多个脉冲中的每一个顺序地施加到选择的存储器 根据执行编程循环的次数来改变多个存储单元之间的单元。 响应于多个脉冲的变化，确定第一禁止电压和第二禁止电压中的至少一个，使得分别施加到未选择的第一和第二禁止电压中的至少一个的电压电平， 连接到多个存储单元之间的未选择的存储单元的第二信号线根据执行编程循环的次数而改变。
-
公开(公告)号：US09183932B1
公开(公告)日：2015-11-10
申请号：US14685671
申请日：2015-04-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyo-Jin Kwon , Yeong-Taek Lee , Dae-Seok Byeon , Yong-Kyu Lee , Hyun-Kook Park
CPC classification number: G11C11/1675 , G11C11/1673 , G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2213/72
Abstract: A resistive memory device including multiple resistive memory cells arranged in regions where first signal lines and second signal lines cross each other, and a method of operating the resistive memory device, are provided. The method includes applying a first voltage to a first line, from among unselected first signal lines connected to unselected memory cells, that is not adjacent to a selected first signal line connected to a selected memory cell from among the multiple memory cells; applying a second voltage that is lower than the first voltage to a second line, from among the unselected first signal lines, that is adjacent to the selected first signal line; floating the unselected first signal lines; and applying a third voltage that is higher than the first voltage to the selected first signal line.
Abstract translation: 一种电阻式存储器件，包括布置在第一信号线和第二信号线彼此交叉的区域中的多个电阻性存储器单元，以及操作该电阻式存储器件的方法。 该方法包括从连接到未选择的存储单元的未选择的第一信号线中的第一行应用第一电压，其不与多个存储器单元中连接到所选择的存储器单元的所选择的第一信号线相邻; 从与所选择的第一信号线相邻的未选择的第一信号线中施加低于第一电压的第二电压到第二线; 浮动未选择的第一条信号线; 以及将高于第一电压的第三电压施加到所选择的第一信号线。
-
公开(公告)号：US09685227B2
公开(公告)日：2017-06-20
申请号：US14661935
申请日：2015-03-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong-Kyu Lee , Yeong-Taek Lee , Dae-Seok Byeon , Hyun-Kook Park , Hyo-Jin Kwon
CPC classification number: G11C13/004 , G11C7/06 , G11C11/1673 , G11C11/56 , G11C11/5607 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0002 , G11C2013/0054 , G11C2213/71
Abstract: A method of reading a memory device that includes a memory cell that stores data of at least two bits includes determining whether a cell resistance level is no greater than a threshold resistance level. If the cell resistance level is smaller than or equal to the threshold resistance level, then the data is read based on a first factor that is inversely proportional to the cell resistance level. If the cell resistance level is greater than the threshold resistance level, then the data is read based on a second factor that is proportional to the cell resistance level.
-
Patent Agency Ranking
6.发明授权公开(公告)号：US09558822B2
公开(公告)日：2017-01-31
申请号：US14695922
申请日：2015-04-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun-Kook Park , Yeong-Taek Lee , Dae-Seok Byeon , Yong-Kyu Lee , Hyo-Jin Kwon
CPC classification number: G11C13/0069 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0064 , G11C2013/0045 , G11C2013/0066 , G11C2013/0073 , G11C2013/0076 , G11C2013/0078 , G11C2013/0088 , G11C2013/0092
Abstract: In operating a resistive memory device including a number of memory cells, a write pulse is applied to each of the plurality of memory cells such that each of the memory cells has a target resistance state between a first reference resistance and a second reference resistance higher than the first reference resistance. The resistance of each of the memory cells is read by applying a verify pulse to each of the plurality of memory cells. A verify write current pulse is applied to each of the memory cells that has resistance higher than the second reference resistance, and a verify write voltage pulse is applied to each of the memory cells that has resistance lower than the first reference resistance.
Abstract translation: 在操作包括多个存储单元的电阻式存储器件时，将写入脉冲施加到多个存储器单元中的每一个，使得每个存储单元具有第一参考电阻和第二参考电阻之间的目标电阻状态， 第一个参考电阻。 通过对多个存储单元中的每一个应用验证脉冲来读取每个存储单元的电阻。 将验证写入电流脉冲施加到具有高于第二参考电阻的电阻的每个存储器单元，并且将验证写电压脉冲施加到具有低于第一参考电阻的电阻的每个存储单元。
-
公开(公告)号：US09558821B2
公开(公告)日：2017-01-31
申请号：US14645701
申请日：2015-03-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun-Kook Park , Dae-Seok Byeon , Yeong-Taek Lee , Hyo-Jin Kwon , Yong-Kyu Lee
CPC classification number: G11C13/0069 , G11C11/1659 , G11C11/1675 , G11C11/5607 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0064 , G11C13/0097 , G11C2013/0076 , G11C2213/71
Abstract: Provided are a resistive memory device and a method of the resistive memory device. The method of operating the resistive memory device includes performing a pre-read operation on memory cells in response to a write command; performing an erase operation on one or more first memory cells on which a reset write operation is to be performed, determined based on a result of comparing pre-read data from the pre-read operation with write data; and performing set-direction programming on at least some memory cells from among the erased one or more first memory cells and on one or more second memory cells on which a set write operation is to be performed.
Abstract translation: 提供了电阻式存储器件和电阻式存储器件的方法。 操作电阻式存储器件的方法包括：响应写入命令对存储器单元执行预读取操作; 基于将来自预读取操作的预读数据与写数据进行比较确定的一个或多个要执行复位写操作的第一存储单元执行擦除操作; 并且对被擦除的一个或多个第一存储器单元中的至少一些存储器单元以及要执行设定写入操作的一个或多个第二存储器单元执行设置方向编程。
-
公开(公告)号：US09171617B1
公开(公告)日：2015-10-27
申请号：US14667993
申请日：2015-03-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun-Kook Park , Yeong-Taek Lee , Dae-Seok Byeon , Yong-Kyu Lee , Hyo-Jin Kwon
CPC classification number: G11C13/0069 , G11C13/0002 , G11C13/0064 , G11C2013/0066 , G11C2013/0076 , G11C2013/0092
Abstract: A method of programming memory cells of a resistive memory device includes; applying a first current pulse to each of the plurality of memory cells; applying a second current pulse that increases by a first difference compared to the first current pulse to each of the plurality of memory cells to which the first current pulse is applied; and applying a third current pulse that increases by a second difference compared to the second current pulse to each of the plurality of memory cells to which the second current pulse is applied, wherein the first through third current pulses non-linearly increase, and the second difference is greater than the first difference.
Abstract translation: 一种编程电阻式存储器件的存储单元的方法包括： 对所述多个存储单元中的每一个施加第一电流脉冲; 将与第一电流脉冲相比增加第一差的第二电流脉冲施加到施加了第一电流脉冲的多个存储单元中的每一个; 以及将与所述第二电流脉冲相比增加第二差的第三电流脉冲施加到施加所述第二电流脉冲的所述多个存储单元中的每一个，其中所述第一至第三电流脉冲非线性增加，并且所述第二电流脉冲 差异大于第一个差异。
-
9.发明授权公开(公告)号：US09646685B2
公开(公告)日：2017-05-09
申请号：US14697229
申请日：2015-04-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun-Kook Park , Yeong-Taek Lee , Dae-Seok Byeon , Yong-Kyu Lee , Hyo-Jin Kwon
CPC classification number: G11C13/0021 , G11C13/0002 , G11C13/0033 , G11C13/0035 , G11C13/0038 , G11C29/021 , G11C29/028 , G11C2029/0407 , G11C2029/5006 , G11C2213/71
Abstract: An operating method for a resistive memory device includes; applying a bias control voltage to a memory cell array of the resistive memory device, measuring leakage current that occurs in the memory cell array in response to the applied bias control voltage to generate a measuring result, generating a control signal based on the measuring result, and adjusting a level of the bias control voltage in response to the control signal.
-
10.发明授权Resistive memory device, resistive memory system and method of operating the resistive memory device 有权电阻式存储器件，电阻式存储器系统和操作电阻式存储器件的方法公开(公告)号：US09449686B2
公开(公告)日：2016-09-20
申请号：US14743488
申请日：2015-06-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyo-Jin Kwon , Yeong-Taek Lee , Dae-Seok Byeon
CPC classification number: G11C13/004 , G11C11/1655 , G11C11/1657 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C13/0069
Abstract: A method of operating a resistive memory device and a resistive memory system including a resistive memory device is for a resistive memory device including a plurality of bit lines and at least one dummy bit line. The method of operating the resistive memory device includes detecting a first address accompanying a first command, generating a plurality of inhibit voltages for biasing non-selected lines, and providing to a first dummy bit line a first inhibit voltage selected from among the plurality of inhibit voltages based on a result of detecting the first address.
Abstract translation: 一种操作电阻式存储器件和包括电阻性存储器件的电阻式存储器系统的方法是用于包括多个位线和至少一个虚拟位线的电阻式存储器件。 操作电阻式存储器件的方法包括检测伴随第一命令的第一地址，产生用于偏置非选择线路的多个禁止电压，以及向第一伪位线提供从多个禁止中选择的第一禁止电压 基于检测到第一地址的结果的电压。
-
-
-
-
-
-
-
-
-
Search Results
19
records
(took 0.017 seconds)
