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公开(公告)号：US09659645B2
公开(公告)日：2017-05-23
申请号：US14665140
申请日：2015-03-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun-Kook Park , Yeong-Taek Lee , Dae-Seok Byeon , Yong-Kyu Lee , Hyo-Jin Kwon
CPC classification number: G11C13/0069 , G11C11/1675 , G11C11/1693 , G11C13/0002 , G11C13/0023 , G11C13/0061 , G11C13/0064 , G11C13/0097 , G11C2213/71
Abstract: A method of writing data in a resistive memory device having a memory cell array divided into first and second tiles includes; performing a first simultaneous write operation by performing a set write operation performed on resistive memory cells of the first tile while simultaneously performing a reset write operation on resistive memory cells of the second tile in response to the write command, and performing a second simultaneous write operation by performing a reset write operation on resistive memory cells of the first tile while simultaneously performing a set write operation on resistive memory cells of the second tile in response to the write command.
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公开(公告)号：US09530494B2
公开(公告)日：2016-12-27
申请号：US14697244
申请日：2015-04-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong-Kyu Lee , Dae-Seok Byeon , Yeong-Taek Lee , Chi-Weon Yoon , Hyun-Kook Park , Hyo-Jin Kwon
CPC classification number: G11C13/0069 , G11C13/0033 , G11C13/0035 , G11C16/10 , G11C2013/0092
Abstract: A method of operating a memory device, which includes of memory cells respectively arranged in regions where first signal lines and second lines cross each other, includes determining a plurality of pulses so that each of the plurality of pulses that are sequentially applied to a selected memory cell among the plurality of memory cells is changed according to a number of times of executing programming loops. In response to the change of the plurality of pulses, at least one of a first inhibit voltage and a second inhibit voltage is determined so that a voltage level of at least one of the first and second inhibit voltages that are respectively applied to unselected first and second signal lines connected to unselected memory cells among the plurality of memory cells is changed according to the number of times of executing the programming loops.
Abstract translation: 一种操作存储器件的方法，所述存储器件包括分别布置在第一信号线和第二线彼此交叉的区域中的存储器单元，包括确定多个脉冲，使得多个脉冲中的每一个顺序地施加到选择的存储器 根据执行编程循环的次数来改变多个存储单元之间的单元。 响应于多个脉冲的变化，确定第一禁止电压和第二禁止电压中的至少一个，使得分别施加到未选择的第一和第二禁止电压中的至少一个的电压电平， 连接到多个存储单元之间的未选择的存储单元的第二信号线根据执行编程循环的次数而改变。
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公开(公告)号：US09508441B1
公开(公告)日：2016-11-29
申请号：US15131237
申请日：2016-04-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Wan Nam , Dae-Seok Byeon , Chi-Weon Yoon
CPC classification number: G11C16/10 , G11C16/0483
Abstract: A memory device includes a memory cell array including a plurality of NAND strings, wherein each of the NAND strings includes a ground selection transistor connected to a ground selection line, memory cells connected to word lines, and a string selection transistor connected to a string selection line, wherein the ground selection line, the word lines, and the string selection line are vertically stacked on a substrate. A control logic adjusts a ground selection line voltage applied to the ground selection line or a string selection line voltage applied to the string selection line to a negative level in at least a portion of a program section during which a program operation related to a memory cell selected from among the memory cells is performed.
Abstract translation: 存储器件包括包括多个NAND串的存储单元阵列，其中每个NAND串包括连接到接地选择线的接地选择晶体管，连接到字线的存储单元和连接到串选择的串选择晶体管 线，其中地面选择线，字线和弦选择线垂直地堆叠在基底上。 控制逻辑在施加到接地选择线的接地选择线电压或施加到串选择线的串选择线电压在程序部分的至少一部分中将与存储器单元相关的程序操作 从存储单元中进行选择。
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公开(公告)号：US09478290B1
公开(公告)日：2016-10-25
申请号：US14938394
申请日：2015-11-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Wan Nam , Kyung-Hwa Kang , Dae-Seok Byeon , Chi-Weon Yoon
CPC classification number: G11C16/0483 , G11C7/14 , G11C8/14 , G11C16/08 , G11C16/26 , G11C16/3427 , H01L27/11575 , H01L27/11582
Abstract: A memory device is provided as follows. A memory cell array includes strings including first and second strings. Each string includes a ground selection transistor and cell transistors. First and second ground selection lines are connected to a gate of a first ground selection transistor of the first string and a gate of a second ground selection transistor of the second string, respectively. First and second cell gate lines are connected to a gate of a first cell transistor of the first string and a gate of a second cell transistor of the second string, respectively. A first interconnection unit electrically connects a first portion of the first cell gate line to a first portion of the second cell gate line. A second interconnection unit electrically connects a second portion of the first cell gate line to a second portion of the second cell gate line.
Abstract translation: 如下提供存储器件。 存储单元阵列包括包括第一和第二串的串。 每个串包括接地选择晶体管和单元晶体管。 第一和第二接地选择线分别连接到第一串的第一接地选择晶体管的栅极和第二串的第二接地选择晶体管的栅极。 第一和第二单元栅极线分别连接到第一串的第一单元晶体管的栅极和第二串的第二单元晶体管的栅极。 第一互连单元将第一单元栅极线的第一部分电连接到第二单元栅极线的第一部分。 第二互连单元将第一单元栅极线的第二部分电连接到第二单元栅极线的第二部分。
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5.发明授权Nonvolatile memory device including dummy wordline, memory system, and method of operating memory system 有权非易失性存储器件包括伪字线，存储器系统和操作存储器系统的方法公开(公告)号：US09367417B2
公开(公告)日：2016-06-14
申请号：US14463130
申请日：2014-08-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Bong-Kil Jung , Dae-Seok Byeon
CPC classification number: G06F11/26 , G11C8/14 , G11C16/3418 , G11C29/42 , G11C29/52 , G11C2029/0411
Abstract: A method of operating a memory system includes reading data of first memory cells, the first memory cells being connected to a first wordline from among a plurality of wordlines, the plurality of wordlines including one or more dummy wordlines and one or more normal wordlines; determining whether the first wordline is one of the one or more dummy wordlines by determining, based on the read data, a number of the first memory cells having a first threshold voltage state, the one or more dummy wordlines being wordlines the memory cells of which have been programmed with dummy data, the one or more normal wordlines being wordlines that are not dummy wordlines; and performing a repair algorithm for correcting an error in the read data, selectively according to a result of the determination.
Abstract translation: 一种操作存储器系统的方法包括读取第一存储器单元的数据，第一存储器单元从多个字线中连接到第一字线，多个字线包括一个或多个虚拟字线和一个或多个正常字线; 通过基于读取的数据确定具有第一阈值电压状态的第一存储器单元的数量，确定第一字线是否是一个或多个虚拟字线中的一个，一个或多个虚拟字线是其存储单元的字母 已经用伪数据编程，一个或多个正常字线是不是伪字线的字线; 以及根据确定的结果选择性地执行用于校正读取数据中的错误的修复算法。
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Patent Agency Ranking
公开(公告)号：US09183932B1
公开(公告)日：2015-11-10
申请号：US14685671
申请日：2015-04-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyo-Jin Kwon , Yeong-Taek Lee , Dae-Seok Byeon , Yong-Kyu Lee , Hyun-Kook Park
CPC classification number: G11C11/1675 , G11C11/1673 , G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2213/72
Abstract: A resistive memory device including multiple resistive memory cells arranged in regions where first signal lines and second signal lines cross each other, and a method of operating the resistive memory device, are provided. The method includes applying a first voltage to a first line, from among unselected first signal lines connected to unselected memory cells, that is not adjacent to a selected first signal line connected to a selected memory cell from among the multiple memory cells; applying a second voltage that is lower than the first voltage to a second line, from among the unselected first signal lines, that is adjacent to the selected first signal line; floating the unselected first signal lines; and applying a third voltage that is higher than the first voltage to the selected first signal line.
Abstract translation: 一种电阻式存储器件，包括布置在第一信号线和第二信号线彼此交叉的区域中的多个电阻性存储器单元，以及操作该电阻式存储器件的方法。 该方法包括从连接到未选择的存储单元的未选择的第一信号线中的第一行应用第一电压，其不与多个存储器单元中连接到所选择的存储器单元的所选择的第一信号线相邻; 从与所选择的第一信号线相邻的未选择的第一信号线中施加低于第一电压的第二电压到第二线; 浮动未选择的第一条信号线; 以及将高于第一电压的第三电压施加到所选择的第一信号线。
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公开(公告)号：US10714183B2
公开(公告)日：2020-07-14
申请号：US16422213
申请日：2019-05-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-Kyu Kim , Young-Sun Min , Dae-Seok Byeon , Ho-Kil Lee
Abstract: A high voltage switch circuit includes a first transistor, a first depletion mode transistor, a level shifter, a control signal generator, a second transistor and a second depletion mode transistor. The first transistor transmits the second driving voltage to an output terminal in response to a first gate signal. The first depletion mode transistor transmits the second driving voltage to the first transistor in response to feedback from the output terminal. The control signal generator generates first and second control signals in response to a level-shifted enable signal. The second transistor has a gate electrode connected to the first voltage and is turned on and off in response to the second control signal at a first end of the second transistor. The second depletion mode transistor is connected between a second end of the second transistor and the output terminal, and has a gate electrode receiving the first control signal.
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公开(公告)号：US10692543B2
公开(公告)日：2020-06-23
申请号：US16363307
申请日：2019-03-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Young-Ho Na , Young-Sun Min , Dae-Seok Byeon
Abstract: A semiconductor package includes first through third memory chips. The first memory chip is arranged on a package substrate, the second memory chip is arranged on the first memory chip, and the third memory chip is arranged between the first memory chip and the second memory chip. Each of the first through third memory chips includes a memory cell array storing data, stress detectors, a stress index generator, and a control circuit. The stress detectors are formed and distributed in a substrate, and detect stacking stress in response to an external voltage to output a plurality of sensing currents. The stress index generator converts the plurality of sensing currents into stress index codes. The control circuit adjusts a value of a feature parameter associated with an operating voltage of a corresponding memory chip, based on at least a portion of the stress index codes.
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公开(公告)号：US09437290B2
公开(公告)日：2016-09-06
申请号：US14631182
申请日：2015-02-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong-Kyu Lee , Dae-Seok Byeon , Hyo-Jin Kwon , Hyun-Kook Park , Chi-Weon Yoon , Yeong-Taek Lee
CPC classification number: G11C13/0033 , G11C11/5607 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007
Abstract: A method of operating a resistive memory device including a plurality of memory cells comprises determining whether to perform a refresh operation on memory cells in a memory cell array; determining a resistance state of each of at least some of the memory cells; and performing a re-writing operation on a first memory cell having a resistance state from among a plurality of resistance states that is equal to or less than a critical resistance level.
Abstract translation: 一种操作包括多个存储单元的电阻式存储器件的方法包括：确定是否对存储单元阵列中的存储器单元执行刷新操作; 确定所述至少一些所述存储器单元中的每一个的电阻状态; 以及在等于或小于临界电阻水平的多个电阻状态之中对具有电阻状态的第一存储单元执行重写操作。
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公开(公告)号：US09613697B2
公开(公告)日：2017-04-04
申请号：US15151661
申请日：2016-05-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun-Kook Park , Yeong-Taek Lee , Dae-Seok Byeon
CPC classification number: G11C13/0069 , G11C11/56 , G11C13/0002 , G11C13/0026 , G11C13/0028 , G11C2013/0078 , G11C2213/15 , G11C2213/71 , G11C2213/72 , G11C2213/79
Abstract: A resistive memory device includes a memory cell array having a plurality of memory cells respectively connected to a plurality of first signal lines and a plurality of second signal lines crossing each other. A first write driver is configured to provide a write voltage to write data to the memory cells. A second write driver is configured to be disposed between the memory cell array and the first write driver and provide a write current generated based on the write voltage to a first signal line selected from among the plurality of first signal lines.
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