Invention Grant
US09570564B2 Self-aligned emitter-base bipolar junction transistor with reduced base resistance and base-collector capacitance
有权
具有降低的基极电阻和基极集电极电容的自对准发射极 - 基极双极结型晶体管
- Patent Title: Self-aligned emitter-base bipolar junction transistor with reduced base resistance and base-collector capacitance
- Patent Title (中): 具有降低的基极电阻和基极集电极电容的自对准发射极 - 基极双极结型晶体管
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Application No.: US14451716Application Date: 2014-08-05
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Publication No.: US09570564B2Publication Date: 2017-02-14
- Inventor: Deborah A. Alperstein , David L. Harame , Alvin J. Joseph , Qizhi Liu , Keith J. Machia , Christa R. Willets
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Thompson Hine LLP
- Agent Anthony Canale
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/417 ; H01L29/732 ; H01L29/08 ; H01L29/10 ; H01L29/423 ; H01L29/737

Abstract:
Device structures and fabrication methods for a bipolar junction transistor. A first semiconductor layer is formed on a substrate containing a first terminal. An etch stop layer is formed on the first semiconductor layer, and a second semiconductor layer is formed on the etch stop layer. The second semiconductor layer is etched to define a second terminal at a location of an etch mask on the second semiconductor layer. A first material comprising the etch stop layer and a second material comprising the second semiconductor layer are selected such that the second material of the second semiconductor layer etches at a greater etch rate than the first material of the etch stop layer. The first semiconductor layer may be a base layer that is used to form an intrinsic base and an extrinsic base of the bipolar junction transistor.
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