公开(公告)号：US09231087B2

公开(公告)日：2016-01-05

申请号：US14677303

申请日：2015-04-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Benoit ,  James R. Elliott ,  Peter B. Gray ,  Alvin J. Joseph ,  Qizhi Liu ,  Christa R. Willets

IPC: H01L29/732 ,  H01L29/66 ,  H01L29/06 ,  H01L29/737

CPC classification number: H01L29/732 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/66272 ,  H01L29/7371 ,  H01L29/7378

Abstract: Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.

公开(公告)号：US09570564B2

公开(公告)日：2017-02-14

申请号：US14451716

申请日：2014-08-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Deborah A. Alperstein ,  David L. Harame ,  Alvin J. Joseph ,  Qizhi Liu ,  Keith J. Machia ,  Christa R. Willets

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/732 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/737

CPC classification number: H01L29/41708 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7371

Abstract: Device structures and fabrication methods for a bipolar junction transistor. A first semiconductor layer is formed on a substrate containing a first terminal. An etch stop layer is formed on the first semiconductor layer, and a second semiconductor layer is formed on the etch stop layer. The second semiconductor layer is etched to define a second terminal at a location of an etch mask on the second semiconductor layer. A first material comprising the etch stop layer and a second material comprising the second semiconductor layer are selected such that the second material of the second semiconductor layer etches at a greater etch rate than the first material of the etch stop layer. The first semiconductor layer may be a base layer that is used to form an intrinsic base and an extrinsic base of the bipolar junction transistor.

Abstract translation: 双极结型晶体管的器件结构和制造方法。 在包含第一端子的基板上形成第一半导体层。 在第一半导体层上形成蚀刻停止层，在蚀刻停止层上形成第二半导体层。 蚀刻第二半导体层以在第二半导体层上的蚀刻掩模的位置处限定第二端子。 选择包括蚀刻停止层的第一材料和包括第二半导体层的第二材料，使得第二半导体层的第二材料以比蚀刻停止层的第一材料更高的蚀刻速率蚀刻。 第一半导体层可以是用于形成双极结型晶体管的本征基极和非本征基极的基极层。