Invention Grant
US09571105B2 System and method for an accuracy-enhanced DLL during a measure initialization mode
有权
测量初始化模式期间精度增强型DLL的系统和方法
- Patent Title: System and method for an accuracy-enhanced DLL during a measure initialization mode
- Patent Title (中): 测量初始化模式期间精度增强型DLL的系统和方法
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Application No.: US14566358Application Date: 2014-12-10
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Publication No.: US09571105B2Publication Date: 2017-02-14
- Inventor: Jongtae Kwak
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: H03L7/06
- IPC: H03L7/06 ; H03L7/08 ; G11C7/10 ; G11C7/22 ; H03L7/081

Abstract:
A clock generator having a delay locked loop and a delay control circuit. The delay locked loop receives an input clock signal and adjusts an adjustable delay circuit to generate an output clock signal that is synchronized with received input clock signal. The delay control circuit coupled to the delay locked loop generates a control signal to initialize the delay measure operation to adjust the adjustable delay circuit, after comparing the phase difference of the input clock signal and the output clock signal. The delay control circuit further generates a start measure control signal to start measuring a delay applied to the measurement signal propagating through the adjustable delay circuit, and generates a stop measure control signal to stop the delay measurement of the measurement signal. The delay adjustment of the delay locked loop is then adjusted to apply the delay measurement when synchronizing the input and output clock signals.
Public/Granted literature
- US20150091624A1 SYSTEM AND METHOD FOR AN ACCURACY-ENHANCED DLL DURING A MEASURE INITIALIZATION MODE Public/Granted day:2015-04-02
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