发明授权
- 专利标题: Voltage droop mitigation in 3D chip system
- 专利标题(中): 3D芯片系统中降压降压
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申请号: US14144920申请日: 2013-12-31
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公开(公告)号: US09595508B2公开(公告)日: 2017-03-14
- 发明人: Yi Xu , Xing Hu , Yuan Xie
- 申请人: Advanced Micro Devices, Inc.
- 申请人地址: US CA Sunnyvale
- 专利权人: Advanced Micro Devices, Inc.
- 当前专利权人: Advanced Micro Devices, Inc.
- 当前专利权人地址: US CA Sunnyvale
- 代理机构: Faegre Baker Daniels LLP
- 优先权: CN201310659511 20131209
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; H01L25/07 ; G06F1/32
摘要:
The present invention relates to a multichip system and a method for scheduling threads in 3D stacked chip. The multichip system comprises a plurality of dies stacked vertically and electrically coupled together; each of the plurality of dies comprising one or more cores, each of the plurality of dies further comprising: at least one voltage violation sensing unit, the at least one voltage violation sensing unit being connected with the one or more cores of each die, the at least one voltage sensing unit being configured to independently sense voltage violation in each core of each die; and at least one frequency tuning unit, the at least one frequency tuning unit being configured to tune the frequency of each core of each die, the at least one frequency tuning unit being connected with the at least one voltage violation sensing unit. The multichip system and method described in present invention have many advantages, such as reducing voltage violation, mitigating voltage droop and saving power.
公开/授权文献
- US20150160975A1 VOLTAGE DROOP MITIGATION IN 3D CHIP SYSTEM 公开/授权日:2015-06-11
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