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公开(公告)号：US20170153916A1
公开(公告)日：2017-06-01
申请号：US15428536
申请日：2017-02-09
Applicant: Advanced Micro Devices, Inc.
IPC: G06F9/48 , H01L25/065
CPC classification number: H01L25/074 , G06F1/329 , G06F9/4881 , G06F17/5031 , G06F17/5045 , G06F2217/78 , G06F2217/84 , H01L23/5286 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2224/73253 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06589 , H01L2924/0002 , H01L2924/15311 , Y02D10/24 , H01L2924/00
Abstract: The present invention relates to a multichip system and a method for scheduling threads in 3D stacked chip. The multichip system comprises a plurality of dies stacked vertically and electrically coupled together; each of the plurality of dies comprising one or more cores, each of the plurality of dies further comprising: at least one voltage violation sensing unit, the at least one voltage violation sensing unit being connected with the one or more cores of each die, the at least one voltage sensing unit being configured to independently sense voltage violation in each core of each die; and at least one frequency tuning unit, the at least one frequency tuning unit being configured to tune the frequency of each core of each die, the at least one frequency tuning unit being connected with the at least one voltage violation sensing unit. The multichip system and method described in present invention have many advantages, such as reducing voltage violation, mitigating voltage droop and saving power.
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公开(公告)号：US09595508B2
公开(公告)日：2017-03-14
申请号：US14144920
申请日：2013-12-31
Applicant: Advanced Micro Devices, Inc.
CPC classification number: H01L25/074 , G06F1/329 , G06F9/4881 , G06F17/5031 , G06F2217/78 , G06F2217/84 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2224/73253 , H01L2924/0002 , H01L2924/15311 , Y02D10/24 , H01L2924/00
Abstract: The present invention relates to a multichip system and a method for scheduling threads in 3D stacked chip. The multichip system comprises a plurality of dies stacked vertically and electrically coupled together; each of the plurality of dies comprising one or more cores, each of the plurality of dies further comprising: at least one voltage violation sensing unit, the at least one voltage violation sensing unit being connected with the one or more cores of each die, the at least one voltage sensing unit being configured to independently sense voltage violation in each core of each die; and at least one frequency tuning unit, the at least one frequency tuning unit being configured to tune the frequency of each core of each die, the at least one frequency tuning unit being connected with the at least one voltage violation sensing unit. The multichip system and method described in present invention have many advantages, such as reducing voltage violation, mitigating voltage droop and saving power.
Abstract translation: 本发明涉及一种多芯片系统和一种在3D堆叠芯片中调度线程的方法。 多芯片系统包括垂直堆叠并电耦合在一起的多个管芯; 所述多个模具中的每一个包括一个或多个芯，所述多个模具中的每一个还包括：至少一个电压违规感测单元，所述至少一个电压违规感测单元与每个裸片的所述一个或多个芯相连接， 至少一个电压感测单元被配置为独立地感测每个管芯的每个铁芯中的电压违例; 以及至少一个频率调谐单元，所述至少一个频率调谐单元经配置以调谐每个芯片的每个芯片的频率，所述至少一个频率调谐单元与所述至少一个电压违规感测单元连接。 本发明中描述的多芯片系统和方法具有许多优点，例如减少电压冲击，降低电压下降和节省功率。
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公开(公告)号：US20150160975A1
公开(公告)日：2015-06-11
申请号：US14144920
申请日：2013-12-31
Applicant: Advanced Micro Devices, Inc.
CPC classification number: H01L25/074 , G06F1/329 , G06F9/4881 , G06F17/5031 , G06F2217/78 , G06F2217/84 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2224/73253 , H01L2924/0002 , H01L2924/15311 , Y02D10/24 , H01L2924/00
Abstract: The present invention relates to a multichip system and a method for scheduling threads in 3D stacked chip. The multichip system comprises a plurality of dies stacked vertically and electrically coupled together; each of the plurality of dies comprising one or more cores, each of the plurality of dies further comprising: at least one voltage violation sensing unit, the at least one voltage violation sensing unit being connected with the one or more cores of each die, the at least one voltage sensing unit being configured to independently sense voltage violation in each core of each die; and at least one frequency tuning unit, the at least one frequency tuning unit being configured to tune the frequency of each core of each die, the at least one frequency tuning unit being connected with the at least one voltage violation sensing unit. The multichip system and method described in present invention have many advantages, such as reducing voltage violation, mitigating voltage droop and saving power.
Abstract translation: 本发明涉及一种多芯片系统和一种在3D堆叠芯片中调度线程的方法。 多芯片系统包括垂直堆叠并电耦合在一起的多个管芯; 所述多个模具中的每一个包括一个或多个芯，所述多个模具中的每一个还包括：至少一个电压违规感测单元，所述至少一个电压违规感测单元与每个裸片的所述一个或多个芯相连接， 至少一个电压感测单元被配置为独立地感测每个管芯的每个铁芯中的电压违例; 以及至少一个频率调谐单元，所述至少一个频率调谐单元经配置以调谐每个芯片的每个芯片的频率，所述至少一个频率调谐单元与所述至少一个电压违规感测单元连接。 本发明中描述的多芯片系统和方法具有许多优点，例如减少电压冲击，降低电压下降和节省功率。
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公开(公告)号：US10361175B2
公开(公告)日：2019-07-23
申请号：US15428536
申请日：2017-02-09
Applicant: Advanced Micro Devices, Inc.
IPC: G06F17/50 , H01L25/07 , G06F1/329 , G06F9/48 , H01L25/065 , H01L23/528
Abstract: The present invention relates to a multichip system and a method for scheduling threads in 3D stacked chip. The multichip system comprises a plurality of dies stacked vertically and electrically coupled together; each of the plurality of dies comprising one or more cores, each of the plurality of dies further comprising: at least one voltage violation sensing unit, the at least one voltage violation sensing unit being connected with the one or more cores of each die, the at least one voltage sensing unit being configured to independently sense voltage violation in each core of each die; and at least one frequency tuning unit, the at least one frequency tuning unit being configured to tune the frequency of each core of each die, the at least one frequency tuning unit being connected with the at least one voltage violation sensing unit. The multichip system and method described in present invention have many advantages, such as reducing voltage violation, mitigating voltage droop and saving power.
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