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    MEMORY SYSTEM WITH REGION-SPECIFIC MEMORY ACCESS SCHEDULING
    2.
    发明申请
    MEMORY SYSTEM WITH REGION-SPECIFIC MEMORY ACCESS SCHEDULING 审中-公开
    具有区域特定存储器访问调度的存储器系统

    公开(公告)号：US20160124873A1

    公开(公告)日：2016-05-05

    申请号：US14891523

    申请日：2013-05-16

    申请人： ADVANCED MICRO DEVICES, INC.

    发明人： Yi Xu ,  Nuwan S. Jayasena ,  Yuan Xie

    IPC分类号： G06F13/16 ,  G06F1/32 ,  G11C7/10

    摘要： An integrated circuit device includes a memory controller coupleable to a memory. The memory controller to schedule memory accesses to regions of the memory based on memory timing parameters specific to the regions. A method includes receiving a memory access request at a memory device. The method further includes accessing, from a timing data store of the memory device, data representing a memory timing parameter specific to a region of the memory cell circuitry targeted by the memory access request. The method also includes scheduling, at the memory controller, the memory access request based on the data.

    摘要翻译： 集成电路装置包括可耦合到存储器的存储器控​​制器。 所述存储器控制器基于所述区域特有的存储器定时参数来调度对所述存储器的区域的存储器访问。 一种方法包括在存储器设备处接收存储器访问请求。 该方法还包括从存储器设备的定时数据存储器访问表示存储器定时参数的特定于存储器访问请求所针对的存储器单元电路区域的数据。 该方法还包括在存储器控制器的基础上调度存储器访问请求。

    Methods and apparatus related to data processors and caches incorporated in data processors
    3.
    发明授权
    Methods and apparatus related to data processors and caches incorporated in data processors 有权
    与数据处理器相关的方法和设备，以及并入数据处理器中的高速缓存

    公开(公告)号：US09317448B2

    公开(公告)日：2016-04-19

    申请号：US13953835

    申请日：2013-07-30

    申请人： Advanced Micro Devices, Inc.

    发明人： Zhe Wang ,  Xie Yuan ,  Junli Gu ,  Yi Xu ,  ShuChang Shan ,  Shuai Mu ,  Ting Cao

    IPC分类号： G06F12/00 ,  G06F12/12 ,  G06F12/08

    CPC分类号： G06F12/123 ,  G06F12/0804 ,  G06F12/12 ,  G06F12/121 ,  G06F2212/1024

    摘要： A cache includes a cache array and a cache controller. The cache array has a multiple number of entries. The cache controller is coupled to the cache array, for storing new entries in the cache array in response to accesses by a data processor, and evicts entries from the cache array according to a cache replacement policy. The cache controller includes a frequent writes predictor for storing frequency information indicating a write back frequency for the multiple number of entries. The cache controller selects a candidate entry for eviction based on both recency information and the frequency information.

    摘要翻译： 高速缓存包括高速缓存阵列和高速缓存控制器。 缓存阵列具有多个条目。 高速缓存控制器被耦合到高速缓存阵列，用于响应于数据处理器的访问来存储高速缓存阵列中的新条目，并根据高速缓存替换策略从高速缓存阵列中取出条目。 高速缓存控制器包括用于存储指示多个条目的回写频率的频率信息的频繁写入预测器。 高速缓存控制器基于新近度信息和频率信息来选择用于驱逐的候选条目。

    METHODS AND APPARATUS RELATED TO DATA PROCESSORS AND CACHES INCORPORATED IN DATA PROCESSORS
    4.
    发明申请
    METHODS AND APPARATUS RELATED TO DATA PROCESSORS AND CACHES INCORPORATED IN DATA PROCESSORS 有权
    与数据处理器中的数据处理器和缓存相关的方法和设备

    公开(公告)号：US20150039836A1

    公开(公告)日：2015-02-05

    申请号：US13953835

    申请日：2013-07-30

    申请人： Advanced Micro Devices, Inc.

    发明人： Zhe Wang ,  Xie Yuan ,  Junli Gu ,  Yi Xu ,  ShuChang Shan ,  Shuai Mu ,  Ting Cao

    IPC分类号： G06F12/12

    CPC分类号： G06F12/123 ,  G06F12/0804 ,  G06F12/12 ,  G06F12/121 ,  G06F2212/1024

    摘要： A cache includes a cache array and a cache controller. The cache array has a multiple number of entries. The cache controller is coupled to the cache array, for storing new entries in the cache array in response to accesses by a data processor, and evicts entries from the cache array according to a cache replacement policy. The cache controller includes a frequent writes predictor for storing frequency information indicating a write back frequency for the multiple number of entries. The cache controller selects a candidate entry for eviction based on both recency information and the frequency information.

    摘要翻译： 高速缓存包括高速缓存阵列和高速缓存控制器。 缓存阵列具有多个条目。 高速缓存控制器被耦合到高速缓存阵列，用于响应于数据处理器的访问来存储高速缓存阵列中的新条目，并根据高速缓存替换策略从高速缓存阵列中取出条目。 高速缓存控制器包括用于存储指示多个条目的回写频率的频率信息的频繁写入预测器。 高速缓存控制器基于新近度信息和频率信息来选择用于驱逐的候选条目。

    Voltage droop mitigation in 3D chip system
    5.
    发明授权
    Voltage droop mitigation in 3D chip system 有权
    3D芯片系统中降压降压

    公开(公告)号：US09595508B2

    公开(公告)日：2017-03-14

    申请号：US14144920

    申请日：2013-12-31

    申请人： Advanced Micro Devices, Inc.

    发明人： Yi Xu ,  Xing Hu ,  Yuan Xie

    IPC分类号： G06F17/50 ,  H01L25/07 ,  G06F1/32

    CPC分类号： H01L25/074 ,  G06F1/329 ,  G06F9/4881 ,  G06F17/5031 ,  G06F2217/78 ,  G06F2217/84 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/0002 ,  H01L2924/15311 ,  Y02D10/24 ,  H01L2924/00

    摘要： The present invention relates to a multichip system and a method for scheduling threads in 3D stacked chip. The multichip system comprises a plurality of dies stacked vertically and electrically coupled together; each of the plurality of dies comprising one or more cores, each of the plurality of dies further comprising: at least one voltage violation sensing unit, the at least one voltage violation sensing unit being connected with the one or more cores of each die, the at least one voltage sensing unit being configured to independently sense voltage violation in each core of each die; and at least one frequency tuning unit, the at least one frequency tuning unit being configured to tune the frequency of each core of each die, the at least one frequency tuning unit being connected with the at least one voltage violation sensing unit. The multichip system and method described in present invention have many advantages, such as reducing voltage violation, mitigating voltage droop and saving power.

    摘要翻译： 本发明涉及一种多芯片系统和一种在3D堆叠芯片中调度线程的方法。 多芯片系统包括垂直堆叠并电耦合在一起的多个管芯; 所述多个模具中的每一个包括一个或多个芯，所述多个模具中的每一个还包括：至少一个电压违规感测单元，所述至少一个电压违规感测单元与每个裸片的所述一个或多个芯相连接， 至少一个电压感测单元被配置为独立地感测每个管芯的每个铁芯中的电压违例; 以及至少一个频率调谐单元，所述至少一个频率调谐单元经配置以调谐每个芯片的每个芯片的频率，所述至少一个频率调谐单元与所述至少一个电压违规感测单元连接。 本发明中描述的多芯片系统和方法具有许多优点，例如减少电压冲击，降低电压下降和节省功率。

    VOLTAGE DROOP MITIGATION IN 3D CHIP SYSTEM
    6.
    发明申请
    VOLTAGE DROOP MITIGATION IN 3D CHIP SYSTEM 有权
    三维芯片系统中的电压降低

    公开(公告)号：US20150160975A1

    公开(公告)日：2015-06-11

    申请号：US14144920

    申请日：2013-12-31

    申请人： Advanced Micro Devices, Inc.

    发明人： Yi Xu ,  Xing Hu ,  Yuan Xie

    IPC分类号： G06F9/48 ,  G05F1/46 ,  H01L25/07

    CPC分类号： H01L25/074 ,  G06F1/329 ,  G06F9/4881 ,  G06F17/5031 ,  G06F2217/78 ,  G06F2217/84 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/0002 ,  H01L2924/15311 ,  Y02D10/24 ,  H01L2924/00

    摘要： The present invention relates to a multichip system and a method for scheduling threads in 3D stacked chip. The multichip system comprises a plurality of dies stacked vertically and electrically coupled together; each of the plurality of dies comprising one or more cores, each of the plurality of dies further comprising: at least one voltage violation sensing unit, the at least one voltage violation sensing unit being connected with the one or more cores of each die, the at least one voltage sensing unit being configured to independently sense voltage violation in each core of each die; and at least one frequency tuning unit, the at least one frequency tuning unit being configured to tune the frequency of each core of each die, the at least one frequency tuning unit being connected with the at least one voltage violation sensing unit. The multichip system and method described in present invention have many advantages, such as reducing voltage violation, mitigating voltage droop and saving power.

    摘要翻译： 本发明涉及一种多芯片系统和一种在3D堆叠芯片中调度线程的方法。 多芯片系统包括垂直堆叠并电耦合在一起的多个管芯; 所述多个模具中的每一个包括一个或多个芯，所述多个模具中的每一个还包括：至少一个电压违规感测单元，所述至少一个电压违规感测单元与每个裸片的所述一个或多个芯相连接， 至少一个电压感测单元被配置为独立地感测每个管芯的每个铁芯中的电压违例; 以及至少一个频率调谐单元，所述至少一个频率调谐单元经配置以调谐每个芯片的每个芯片的频率，所述至少一个频率调谐单元与所述至少一个电压违规感测单元连接。 本发明中描述的多芯片系统和方法具有许多优点，例如减少电压冲击，降低电压下降和节省功率。

    Memory system with region-specific memory access scheduling
    7.
    发明授权
    Memory system with region-specific memory access scheduling 有权

    公开(公告)号：US11474703B2

    公开(公告)日：2022-10-18

    申请号：US17199949

    申请日：2021-03-12

    申请人： ADVANCED MICRO DEVICES, INC.

    发明人： Yi Xu ,  Nuwan S. Jayasena ,  Yuan Xie

    IPC分类号： G06F3/06 ,  G06F13/16 ,  G06F12/02 ,  G06F13/42 ,  G06F1/3203 ,  G11C7/10

    摘要： An integrated circuit device includes a memory controller coupleable to a memory. The memory controller to schedule memory accesses to regions of the memory based on memory timing parameters specific to the regions. A method includes receiving a memory access request at a memory device. The method further includes accessing, from a timing data store of the memory device, data representing a memory timing parameter specific to a region of the memory cell circuitry targeted by the memory access request. The method also includes scheduling, at the memory controller, the memory access request based on the data.

    Method and apparatus related to cache memory
    9.
    发明授权
    Method and apparatus related to cache memory 有权
    与缓存相关的方法和装置

    公开(公告)号：US09552301B2

    公开(公告)日：2017-01-24

    申请号：US13942291

    申请日：2013-07-15

    申请人： Advanced Micro Devices, Inc.

    发明人： Zhe Wang ,  Junli Gu ,  Yi Xu

    IPC分类号： G06F12/12 ,  G06F12/08

    CPC分类号： G06F12/0891 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0864 ,  G06F12/12 ,  G06F12/123 ,  G06F12/126

    摘要： A cache includes a cache array and a cache controller. The cache array has a plurality of entries. The cache controller is coupled to the cache array. The cache controller evicts entries from the cache array according to a cache replacement policy. The cache controller evicts a first cache line from the cache array by generating a writeback request for modified data from the first cache line, and subsequently generates a writeback request for modified data from a second cache line if the second cache line is about to satisfy the cache replacement policy and stores data from a common locality as the first cache line.

    摘要翻译： 高速缓存包括高速缓存阵列和高速缓存控制器。 高速缓存阵列具有多个条目。 缓存控制器耦合到高速缓存阵列。 高速缓存控制器根据高速缓存替换策略从高速缓存阵列中排除条目。 高速缓存控制器通过从第一高速缓存行产生对修改数据的回写请求，从高速缓冲存储器阵列中驱除第一高速缓存行，并且随后如果第二高速缓存行即将满足第二高速缓存行，则从第二高速缓存行生成对修改数据的回写请求 高速缓存替换策略并将来自公共位置的数据存储为第一高速缓存行。