Invention Grant
- Patent Title: Reset selection cell to mitigate initialization time
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Application No.: US14581296Application Date: 2014-12-23
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Publication No.: US09602107B2Publication Date: 2017-03-21
- Inventor: Saket Jalan , Abhishek Ganapati Karkisaval
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Lawrence J. Bassuk; Charles A. Brill; Frank D. Cimino
- Main IPC: H03K3/02
- IPC: H03K3/02 ; H03K19/173 ; H03K3/037
Abstract:
A circuit includes a state capture device to capture a logic state of a reset selection cell in response to a logic state input. A cell reset node defines a reset state of the reset selection cell. A selection device passes the captured logic state from the state capture device or the reset state from the cell reset node to an output of the reset selection cell based on a state of a control input to the selection device.
Public/Granted literature
- US20160182020A1 RESET SELECTION CELL TO MITIGATE INITIALIZATION TIME Public/Granted day:2016-06-23
Information query
IPC分类:
