公开(公告)号：US09904595B1

公开(公告)日：2018-02-27

申请号：US15244739

申请日：2016-08-23

Applicant: Texas Instruments Incorporated

Inventor： Saket Jalan ,  Indu Prathapan ,  Abhishek Ganapati Karkisaval

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G11C29/52

Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.

公开(公告)号：US09602107B2

公开(公告)日：2017-03-21

申请号：US14581296

申请日：2014-12-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saket Jalan ,  Abhishek Ganapati Karkisaval

IPC: H03K3/02 ,  H03K19/173 ,  H03K3/037

CPC classification number: H03K19/1737 ,  H03K3/037

Abstract: A circuit includes a state capture device to capture a logic state of a reset selection cell in response to a logic state input. A cell reset node defines a reset state of the reset selection cell. A selection device passes the captured logic state from the state capture device or the reset state from the cell reset node to an output of the reset selection cell based on a state of a control input to the selection device.

公开(公告)号：US11372715B2

公开(公告)日：2022-06-28

申请号：US16790444

申请日：2020-02-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saket Jalan ,  Indu Prathapan ,  Abhishek Ganapati Karkisaval

IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06 ,  G11C29/52

Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.

公开(公告)号：US20220283899A1

公开(公告)日：2022-09-08

申请号：US17824605

申请日：2022-05-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saket Jalan ,  Indu Prathapan ,  Abhishek Ganapati Karkisaval

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.

公开(公告)号：US11740968B2

公开(公告)日：2023-08-29

申请号：US17824605

申请日：2022-05-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saket Jalan ,  Indu Prathapan ,  Abhishek Ganapati Karkisaval

IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F3/064 ,  G06F3/0619 ,  G06F3/0673 ,  G06F11/1012 ,  G06F11/1048 ,  G11C29/52

Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.

公开(公告)号：US20200210287A1

公开(公告)日：2020-07-02

申请号：US16790444

申请日：2020-02-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saket Jalan ,  Indu Prathapan ,  Abhishek Ganapati Karkisaval

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06

Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.

公开(公告)号：US20160182020A1

公开(公告)日：2016-06-23

申请号：US14581296

申请日：2014-12-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saket Jalan ,  Abhishek Ganapati Karkisaval

IPC: H03K3/027

CPC classification number: H03K19/1737 ,  H03K3/037

Abstract: A circuit includes a state capture device to capture a logic state of a reset selection cell in response to a logic state input. A cell reset node defines a reset state of the reset selection cell. A selection device passes the captured logic state from the state capture device or the reset state from the cell reset node to an output of the reset selection cell based on a state of a control input to the selection device.

Abstract translation: 电路包括状态捕捉装置，以响应于逻辑状态输入来捕获复位选择单元的逻辑状态。 单元复位节点定义复位选择单元的复位状态。 选择装置基于向选择装置输入的控制状态，将捕捉到的状态从状态捕获装置或复位状态从小区重置节点传送到复位选择小区的输出。