公开(公告)号：US20210148976A1

公开(公告)日：2021-05-20

申请号：US17160461

申请日：2021-01-28

Applicant: Texas Instruments Incorporated

Inventor： Sundarrajan Rangachari ,  Saket Jalan

IPC: G01R31/319 ,  G01R31/317 ,  G01R31/3177

Abstract: Methods and apparatus for self test of safety logic in safety critical devices is provided in which the safety logic includes comparator logic coupled to a circuit under test (CUT) in a safety critical device and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.

公开(公告)号：US10776546B2

公开(公告)日：2020-09-15

申请号：US16410391

申请日：2019-05-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Wilson Pradeep ,  Prakash Narayanan ,  Saket Jalan

IPC: G06F17/50 ,  G01R27/28 ,  G01R31/28 ,  G01R31/36 ,  G06G7/62 ,  G06F30/3312 ,  G06F30/30 ,  G06F30/398 ,  H01L23/58 ,  H01L25/00 ,  H01L29/10 ,  H03K19/00 ,  G06F30/392 ,  G06F30/394

Abstract: A circuit includes a false circuit path in a circuit under test having a starting logic point to an end logic point of the path. The false circuit path is designated as a testing path to be excluded during testing of one or more valid timing paths of the circuit under test. A false path gating circuit gates the starting logic point to the end logic point of the false circuit path. The false path gating circuit disables the false circuit path in response to one or more gating controls asserted during the testing of the one or more valid timing paths of the circuit under test.

公开(公告)号：US09602107B2

公开(公告)日：2017-03-21

申请号：US14581296

申请日：2014-12-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saket Jalan ,  Abhishek Ganapati Karkisaval

IPC: H03K3/02 ,  H03K19/173 ,  H03K3/037

CPC classification number: H03K19/1737 ,  H03K3/037

Abstract: A circuit includes a state capture device to capture a logic state of a reset selection cell in response to a logic state input. A cell reset node defines a reset state of the reset selection cell. A selection device passes the captured logic state from the state capture device or the reset state from the cell reset node to an output of the reset selection cell based on a state of a control input to the selection device.

公开(公告)号：US11631454B2

公开(公告)日：2023-04-18

申请号：US16744412

申请日：2020-01-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saket Jalan ,  Sudesh Chandra Srivastava ,  Mohammed Nabeel

IPC: G11C11/418 ,  G06F13/16 ,  G06F13/40 ,  G11C11/419 ,  G06F11/10 ,  G11C11/50

Abstract: In described examples, an apparatus includes: a set of control registers containing control bits for controlling circuitry coupled to receive register write enable signals and to receive input data; a memory for storing data corresponding to the control bits coupled to receive an address and a memory write enable signal; decode circuitry coupled to output the register write enable signals; a data output bus coupled to receive data from the memory but free from connections to the control registers; and a controller coupled to receive an address, coupled to output the address on an internal address bus, coupled to output a register write enable signal, and coupled to output the memory write enable signal, configured to cause data to be written to a selected control register corresponding to the address received, and to cause the data to be contemporaneously stored at a memory location corresponding to the address received.

公开(公告)号：US10935602B2

公开(公告)日：2021-03-02

申请号：US15973257

申请日：2018-05-07

Applicant: Texas Instruments Incorporated

Inventor： Sundarrajan Rangachari ,  Saket Jalan

IPC: G01R31/319 ,  G01R31/317 ,  G01R31/3177

Abstract: Methods and apparatus for self test of safety logic in safety critical devices is provided in which the safety logic includes comparator logic coupled to a circuit under test (CUT) in a safety critical device and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.

公开(公告)号：US09964597B2

公开(公告)日：2018-05-08

申请号：US15255044

申请日：2016-09-01

Applicant: Texas Instruments Incorporated

Inventor： Sundarrajan Rangachari ,  Saket Jalan

IPC: G01R31/319 ,  G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31901 ,  G01R31/31701 ,  G01R31/31703 ,  G01R31/31724 ,  G01R31/31727 ,  G01R31/3177

Abstract: Methods and apparatus for self test of safety logic in safety critical devices is provided in which the safety logic includes comparator logic coupled to a circuit under test (CUT) in a safety critical device and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.

公开(公告)号：US09904595B1

公开(公告)日：2018-02-27

申请号：US15244739

申请日：2016-08-23

Applicant: Texas Instruments Incorporated

Inventor： Saket Jalan ,  Indu Prathapan ,  Abhishek Ganapati Karkisaval

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G11C29/52

Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.

公开(公告)号：US11372715B2

公开(公告)日：2022-06-28

申请号：US16790444

申请日：2020-02-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saket Jalan ,  Indu Prathapan ,  Abhishek Ganapati Karkisaval

IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06 ,  G11C29/52

Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.

公开(公告)号：US20200152261A1

公开(公告)日：2020-05-14

申请号：US16744412

申请日：2020-01-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saket Jalan ,  Sudesh Chandra Srivastava ,  Mohammed Nabeel

IPC: G11C11/418 ,  G06F11/10 ,  G11C11/419 ,  G06F13/40 ,  G06F13/16

Abstract: In described examples, an apparatus includes: a set of control registers containing control bits for controlling circuitry coupled to receive register write enable signals and to receive input data; a memory for storing data corresponding to the control bits coupled to receive an address and a memory write enable signal; decode circuitry coupled to output the register write enable signals; a data output bus coupled to receive data from the memory but free from connections to the control registers; and a controller coupled to receive an address, coupled to output the address on an internal address bus, coupled to output a register write enable signal, and coupled to output the memory write enable signal, configured to cause data to be written to a selected control register corresponding to the address received, and to cause the data to be contemporaneously stored at a memory location corresponding to the address received.

公开(公告)号：US10559351B2

公开(公告)日：2020-02-11

申请号：US15437253

申请日：2017-02-20

Applicant: Texas Instruments Incorporated

Inventor： Saket Jalan ,  Sudesh Chandra Srivastava ,  Mohammed Nabeel

IPC: G11C11/418 ,  G06F13/16 ,  G06F13/40 ,  G11C11/42

Abstract: In described examples, an apparatus includes: a set of control registers containing control bits for controlling circuitry coupled to receive register write enable signals and to receive input data; a memory for storing data corresponding to the control bits coupled to receive an address and a memory write enable signal; decode circuitry coupled to output the register write enable signals; a data output bus coupled to receive data from the memory but free from connections to the control registers; and a controller coupled to receive an address, coupled to output the address on an internal address bus, coupled to output a register write enable signal, and coupled to output the memory write enable signal, configured to cause data to be written to a selected control register corresponding to the address received, and to cause the data to be contemporaneously stored at a memory location corresponding to the address received.