Invention Grant
- Patent Title: Patterning approach for improved via landing profile
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Application No.: US15088292Application Date: 2016-04-01
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Publication No.: US09640435B2Publication Date: 2017-05-02
- Inventor: Chih-Yuan Ting , Chung-Wen Wu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L21/4763
- IPC: H01L21/4763 ; H01L21/768 ; H01L23/522 ; H01L23/532

Abstract:
The present disclosure is directed to a semiconductor structure and a method of manufacturing a semiconductor structure in which a spacer element is formed adjacent to a metal body embedded in a first dielectric layer of a first interconnect layer. A via which is misaligned relative to an edge of the metal body is formed in a second dielectric material in second interconnect layer disposed over the first interconnect layer and filled with a conductive material which is electrically coupled to the metal body. The method allows for formation of an interconnect structure without encountering the various problems presented by via substructure defects in the dielectric material of the first interconnect layer, as well as eliminating conventional gap-fill metallization issues.
Public/Granted literature
- US20160218038A1 NOVEL PATTERNING APPROACH FOR IMPROVED VIA LANDING PROFILE Public/Granted day:2016-07-28
Information query
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