Invention Grant
- Patent Title: Block level patterning process
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Application No.: US14699122Application Date: 2015-04-29
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Publication No.: US09646884B2Publication Date: 2017-05-09
- Inventor: Chanro Park , Sukwon Hong , Hoon Kim , Min Gyu Sung
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Ditthavong & Steiner, P.C.
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L21/3213 ; H01L21/027 ; H01L21/28

Abstract:
The present application relates to an optical planarizing layer etch process. Embodiments include forming fins separated by a dielectric layer; forming a recess in the dielectric layer on each side of each fin, each recess being for a metal gate; forming sidewall spacers on each side of each recess; depositing a high-k dielectric liner in each recess and on a top surface of each of the fins; depositing a metal liner over the high-k dielectric layer; depositing a non-conformal organic layer (NCOL) over a top surface of the dielectric layer to pinch-off a top of each recess; depositing an OPL and ARC over the NCOL; etching the OPL, ARC and NCOL over a portion of the dielectric layer and recesses in a first region; and etching the portion of the recesses to remove residual NCOL present at a bottom of each recess of the portion of the recesses.
Public/Granted literature
- US20160322260A1 BLOCK LEVEL PATTERNING PROCESS Public/Granted day:2016-11-03
Information query
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