公开(公告)号：US10446653B2

公开(公告)日：2019-10-15

申请号：US15351893

申请日：2016-11-15

申请人： GLOBALFOUNDRIES Inc.

发明人： Ruilong Xie ,  Min Gyu Sung ,  Chanro Park ,  Lars Wolfgang Liebmann ,  Hoon Kim

IPC分类号： H01L29/417 ,  H01L29/66 ,  H01L29/772 ,  H01L29/49 ,  H01L29/78 ,  H01L21/768

摘要： A semiconductor structure includes a semiconductor substrate, a semiconductor fin on the semiconductor substrate, a transistor integrated with the semiconductor fin at a top portion thereof, the transistor including an active region including a source, a drain and a channel region therebetween. The semiconductor structure further includes a gate structure over the channel region, the gate structure including a gate electrode, an air-gap spacer pair on opposite sidewalls of the gate electrode, and a gate contact for the gate electrode. A method of fabricating such a semiconductor device is also provided.

公开(公告)号：US10319627B2

公开(公告)日：2019-06-11

申请号：US15376831

申请日：2016-12-13

申请人： GLOBALFOUNDRIES Inc.

发明人： Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Ruilong Xie

IPC分类号： H01L21/76 ,  H01L21/768 ,  H01L29/66

摘要： Structures for air-gap spacers in a field-effect transistor and methods for forming air-gap spacers in a field-effect transistor. A gate structure is formed on a top surface of a semiconductor body. A dielectric spacer is formed adjacent to a vertical sidewall of the gate structure. A semiconductor layer is formed on the top surface of the semiconductor body. The semiconductor layer is arranged relative to the vertical sidewall of the gate structure such that a first section of the first dielectric spacer is located in a space between the semiconductor layer and the vertical sidewall of the gate structure. A second section of the dielectric spacer that is located above a top surface of the semiconductor layer is removed. An air-gap spacer is formed in a space from which the second section of the dielectric spacer is removed.

公开(公告)号：US10236291B2

公开(公告)日：2019-03-19

申请号：US15801023

申请日：2017-11-01

申请人： GLOBALFOUNDRIES INC.

发明人： Min Gyu Sung ,  Chanro Park ,  Hoon Kim ,  Ruilong Xie ,  Kwan-Yong Lim

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L21/32 ,  H01L21/311 ,  H01L21/302 ,  H01L21/461 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/78

摘要： At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having an oxide level in a fin array region within a predetermined height of the oxide level of a field region. A first oxide process is performed for controlling a first oxide recess level in a field region adjacent to a fin array region comprising a plurality of fins in a finFET device. The first oxide process comprises depositing an oxide layer over the field region and the fin array region and performing an oxide recess process to bring the oxide layer to the first oxide recess level in the field region. A second oxide process is performed for controlling a second oxide recess level in the fin array region. The second oxide process comprises isolating the fin array region, depositing oxide material, and performing an oxide recess process to bring the oxide level in the fin array region to the second oxide recess level. The first oxide recess level is within a predetermined height differential of the second oxide recess level.

公开(公告)号：US10176996B2

公开(公告)日：2019-01-08

申请号：US14452606

申请日：2014-08-06

申请人： GLOBALFOUNDRIES Inc.

发明人： Min Gyu Sung ,  Chanro Park ,  Hoon Kim

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/49 ,  H01L27/092 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/51

摘要： Embodiments of the present invention provide a replacement metal gate and a fabrication process with reduced lithography steps. Using selective etching techniques, a layer of fill metal is used to protect the dielectric layer in the trenches, eliminating the need for some lithography steps. This, in turn, reduces the overall cost and complexity of fabrication. Furthermore, additional protection is provided during etching, which serves to improve product yield.

公开(公告)号：US10170617B2

公开(公告)日：2019-01-01

申请号：US15424379

申请日：2017-02-03

申请人： GLOBALFOUNDRIES INC.

发明人： Jiseok Kim ,  Hiroaki Niimi ,  Hoon Kim ,  Puneet Harischandra Suvarna ,  Steven Bentley ,  Jody A. Fronheiser

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/36 ,  H01L29/66 ,  H01L29/417

摘要： The present disclosure relates to semiconductor structures and, more particularly, to vertical transport field effect transistor devices and methods of manufacture. A structure includes: a vertical fin structure having a lower dopant region, an upper dopant region and a channel region between the lower dopant region and the upper dopant region; and a doped semiconductor material provided on sides of the vertical fin structure at a lower portion. The lower dopant region being composed of the doped semiconductor material which is merged into the vertical fin structure at the lower portion.

公开(公告)号：US20180342427A1

公开(公告)日：2018-11-29

申请号：US15602225

申请日：2017-05-23

申请人： GLOBALFOUNDRIES INC.

发明人： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Hui Zang ,  Guowei Xu

IPC分类号： H01L21/8238 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L21/823878 ,  B82Y10/00 ,  H01L21/02603 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

摘要： This disclosure relates to a method of replacement metal gate patterning for nanosheet devices including: forming a first and a second nanosheet stack on a substrate, the first and the second nanosheet stacks being adjacent to each other and each including vertically adjacent nanosheets separated by a distance; depositing a first metal surrounding the first nanosheet stack and a second portion of the first metal surrounding the second nanosheet stack; forming an isolation region between the first nanosheet stack and the second nanosheet stack; removing the second portion of the first metal surrounding the second nanosheet stack with an etching process, the isolation region preventing the etching process from reaching the first portion of the first metal and thereby preventing removal of the first portion of the first metal; and depositing a second metal surrounding each of the nanosheets of the second nanosheet stack.

公开(公告)号：US10008577B2

公开(公告)日：2018-06-26

申请号：US15225152

申请日：2016-08-01

申请人： GLOBALFOUNDRIES Inc.

发明人： Ruilong Xie ,  Min Gyu Sung ,  Chanro Park ,  Hoon Kim

IPC分类号： H01L27/00 ,  H01L21/00 ,  H01L29/49 ,  H01L23/535 ,  H01L29/06 ,  H01L29/40 ,  H01L21/768

CPC分类号： H01L29/4991 ,  H01L21/764 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/66795 ,  H01L29/785

摘要： One illustrative method disclosed herein includes, among other things, forming a gate structure above an active region and an isolation region, wherein the gate structure comprises a gate, a first gate cap layer and a first sidewall spacer, removing portions of the first gate cap layer and the first sidewall spacer that are positioned above the active region, while leaving portions of the first gate cap layer and the first sidewall spacer positioned above the isolation region in place, wherein a plurality of spacer cavities are defined adjacent the gate, and forming a replacement air-gap spacer in each of the spacer cavities adjacent the gate and a replacement gate cap layer above the gate, wherein the replacement air-gap spacer comprises an air gap.

公开(公告)号：US10002932B2

公开(公告)日：2018-06-19

申请号：US15345137

申请日：2016-11-07

申请人： GLOBALFOUNDRIES Inc.

发明人： Ruilong Xie ,  Min Gyu Sung ,  Hoon Kim ,  Chanro Park

IPC分类号： H01L29/417 ,  H01L21/8234 ,  H01L21/3205 ,  H01L29/45 ,  H01L21/3105 ,  H01L27/088 ,  H01L29/66

CPC分类号： H01L29/41791 ,  H01L21/0332 ,  H01L21/31051 ,  H01L21/32053 ,  H01L21/76829 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/665

摘要： A method includes providing a starting structure, the starting structure including a semiconductor substrate, sources and drains, a hard mask liner layer over the sources and drains, a bottom dielectric layer over the hard mask liner layer, metal gates between the sources and drains, the metal gates defined by spacers, gate cap openings between corresponding spacers and above the metal gates, and a top dielectric layer above the bottom dielectric layer and in the gate cap openings, resulting in gate caps. The method further includes removing portions of the top dielectric layer, the removing resulting in contact openings and divot(s) at a top portion of the spacers and/or gate caps, and filling the divot(s) with etch-stop material, the etch-stop material having an etch-stop ability better than a material of the spacers and gate cap. A resulting semiconductor structure is also disclosed.

公开(公告)号：US20180130895A1

公开(公告)日：2018-05-10

申请号：US15345644

申请日：2016-11-08

申请人： GLOBALFOUNDRIES Inc.

发明人： Chanro Park ,  Steven Bentley ,  Hoon Kim ,  Min Gyu Sung ,  Ruilong Xie

IPC分类号： H01L29/66 ,  H01L21/3213 ,  H01L21/288 ,  H01L21/321

CPC分类号： H01L29/66666 ,  H01L21/288 ,  H01L21/32136 ,  H01L21/823456 ,  H01L21/823487 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823885 ,  H01L29/7827

摘要： One illustrative method of forming a vertical transistor device disclosed herein includes, among other things, forming bottom source/drain (S/D) regions. A plurality of vertically oriented channel semiconductor structures is formed above the bottom source/drain (S/D) regions. A gate insulation layer is formed above the vertically oriented channel semiconductor structures. A conformal layer of conductive gate material is formed above the gate insulation layer. The conformal layer of conductive material is etched to define conductive gate spacers on sidewalls of the vertically oriented channel semiconductor structures. Top source/drain (S/D) regions are formed above the vertically oriented channel semiconductor structures.

公开(公告)号：US09859125B2

公开(公告)日：2018-01-02

申请号：US15072626

申请日：2016-03-17

申请人： GLOBALFOUNDRIES Inc.

发明人： Min Gyu Sung ,  Ruilong Xie ,  Chanro Park ,  Hoon Kim ,  Kwan-Yong Lim

IPC分类号： H01L21/311 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/11 ,  H01L29/06 ,  H01L29/161

CPC分类号： H01L21/3065 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/11 ,  H01L28/00 ,  H01L29/0642 ,  H01L29/0657 ,  H01L29/161

摘要： Methodologies and a device for SRAM patterning are provided. Embodiments include forming a spacer layer over a fin channel, the fin channel being formed in four different device regions; forming a bottom mandrel over the spacer layer; forming a top mandrel directly over the bottom mandrel, wherein the top and bottom mandrels including different materials; forming a buffer oxide layer over the top mandrel; forming an anti-reflective coating (ARC) over the first OPL; forming a photoresist (PR) over the ARC and patterning the PR; and etching the first OPL, ARC, buffer oxide, and top mandrel with the pattern of the PR, wherein a pitch of the PR as patterned is different in each of the four device regions.