Invention Grant
- Patent Title: Power-aware CPU power grid design
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Application No.: US15173004Application Date: 2016-06-03
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Publication No.: US09658671B2Publication Date: 2017-05-23
- Inventor: Harshit Tiwari , Akshay Kumar Gupta , Srinivas Turaga , Deva Sudhir Kumar Pulivendula , Venkata Devarasetty
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Arent Fox, LLP
- Main IPC: G11C5/14
- IPC: G11C5/14 ; G06F1/26 ; G06F12/0811

Abstract:
A method and an apparatus for providing a power grid are provided. The apparatus includes a plurality of memory units comprising at least one SoC memory and at least one cache memory. The apparatus includes a first subsystem coupled to the at least one SoC memory associated with a first power domain. The apparatus further includes a second subsystem coupled to the at least one cache memory associated with a second power domain. The second subsystem may be a CPU subsystem. Because the first power domain sources power from a shared power source, the first power domain may operate at a voltage level that is higher than the operation of memory circuits requires. By moving the at least one cache memory from the first power domain to the second power domain, LDO efficiency loss for components in the first power domain may be reduced.
Public/Granted literature
- US20170090539A1 POWER-AWARE CPU POWER GRID DESIGN Public/Granted day:2017-03-30
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