公开(公告)号：US10528117B2

公开(公告)日：2020-01-07

申请号：US14579660

申请日：2014-12-22

Applicant: QUALCOMM Incorporated

Inventor： Nikesh Gupta ,  Harshit Tiwari ,  Ashish Bajaj ,  Maheshwar Thakur Singh

IPC: G06F1/3296 ,  G06F1/3287 ,  H04W52/02 ,  G06F1/20 ,  G06F1/3206 ,  G06F1/3234

Abstract: A method of thermal mitigation in a device having a plurality of non-real-time processing units (PUs) and a plurality of real-time PUs, including connecting each of the plurality of real-time PUs and the plurality of non-real-time PUs to a first power supply, and performing thermal mitigation. Performing thermal mitigation includes disconnecting each of the plurality of non-real-time PUs except one of the plurality of non-real-time PUs from the first power supply resulting in an active non-real-time PU, and connecting a second power supply that derives power from the first power supply to the active non-real-time PU, wherein a voltage supplied by the second power supply is less than a voltage supplied by the first power supply.

公开(公告)号：US09582068B2

公开(公告)日：2017-02-28

申请号：US14630392

申请日：2015-02-24

Applicant: QUALCOMM Incorporated

Inventor： Harshit Tiwari ,  Maheshwar Thakur Singh ,  Ashish Bajaj ,  Nikesh Gupta

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3243 ,  G06F1/3265 ,  G06F1/3293 ,  G06F1/3296 ,  Y02D10/152 ,  Y02D10/171

Abstract: Methods, systems, and circuits for preserving state information during power saving operations are disclosed. One example embodiment includes a circuit having a processing core, where the processing core includes logic processing circuits as well as circuits (e.g., flip-flops registers) that are used to store state information in the processing core. The logic processing circuits have power connections to a power rail that are subject to a switch, which can disconnect the power connections from the power rail. The circuits that are used to store state information have different power connections that are subject to a different switch. Therefore, the logic processing circuits and the state information circuits can be separately power-collapsed.

Abstract translation: 公开了用于在省电操作期间保持状态信息的方法，系统和电路。 一个示例实施例包括具有处理核心的电路，其中处理核心包括逻辑处理电路以及用于在处理核心中存储状态信息的电路（例如，触发器寄存器）。 逻辑处理电路具有经受切换的电力轨的电​​力连接，这可以将电力连接从电力轨道断开。 用于存储状态信息的电路具有不同的电源连接，这些电源连接受不同的开关的影响。 因此，逻辑处理电路和状态信息电路可以单独断电。

公开(公告)号：US20160246356A1

公开(公告)日：2016-08-25

申请号：US14630392

申请日：2015-02-24

Applicant: QUALCOMM Incorporated

Inventor： Harshit Tiwari ,  Maheshwar Thakur Singh ,  Ashish Bajaj ,  Nikesh Gupta

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3243 ,  G06F1/3265 ,  G06F1/3293 ,  G06F1/3296 ,  Y02D10/152 ,  Y02D10/171

Abstract: Methods, systems, and circuits for preserving state information during power saving operations are disclosed. One example embodiment includes a circuit having a processing core, where the processing core includes logic processing circuits as well as circuits (e.g., flip-flops registers) that are used to store state information in the processing core. The logic processing circuits have power connections to a power rail that are subject to a switch, which can disconnect the power connections from the power rail. The circuits that are used to store state information have different power connections that are subject to a different switch. Therefore, the logic processing circuits and the state information circuits can be separately power-collapsed.

Abstract translation: 公开了用于在省电操作期间保持状态信息的方法，系统和电路。 一个示例实施例包括具有处理核心的电路，其中处理核心包括逻辑处理电路以及用于在处理核心中存储状态信息的电路（例如，触发器寄存器）。 逻辑处理电路具有经受切换的电力轨的电​​力连接，这可以将电力连接从电力轨道断开。 用于存储状态信息的电路具有不同的电源连接，这些电源连接受不同的开关的影响。 因此，逻辑处理电路和状态信息电路可以单独断电。

公开(公告)号：US09658671B2

公开(公告)日：2017-05-23

申请号：US15173004

申请日：2016-06-03

Applicant: QUALCOMM Incorporated

Inventor： Harshit Tiwari ,  Akshay Kumar Gupta ,  Srinivas Turaga ,  Deva Sudhir Kumar Pulivendula ,  Venkata Devarasetty

IPC: G11C5/14 ,  G06F1/26 ,  G06F12/0811

CPC classification number: G06F1/266 ,  G06F1/32 ,  G06F12/0811 ,  G06F2212/60 ,  G06F2212/62 ,  G06F2213/0038 ,  G11C5/14

Abstract: A method and an apparatus for providing a power grid are provided. The apparatus includes a plurality of memory units comprising at least one SoC memory and at least one cache memory. The apparatus includes a first subsystem coupled to the at least one SoC memory associated with a first power domain. The apparatus further includes a second subsystem coupled to the at least one cache memory associated with a second power domain. The second subsystem may be a CPU subsystem. Because the first power domain sources power from a shared power source, the first power domain may operate at a voltage level that is higher than the operation of memory circuits requires. By moving the at least one cache memory from the first power domain to the second power domain, LDO efficiency loss for components in the first power domain may be reduced.

公开(公告)号：US11340689B2

公开(公告)日：2022-05-24

申请号：US16674494

申请日：2019-11-05

Applicant: QUALCOMM Incorporated

Inventor： Nikesh Gupta ,  Harshit Tiwari ,  Ashish Bajaj ,  Maheshwar Thakur Singh

IPC: G06F1/3287 ,  G06F1/3296 ,  H04W52/02 ,  G06F1/3234 ,  G06F1/20 ,  G06F1/3206

Abstract: A method of thermal mitigation in a device having a plurality of non-real-time processing units (PUs) and a plurality of real-time PUs, including connecting each of the plurality of real-time PUs and the plurality of non-real-time PUs to a first power supply, and performing thermal mitigation. Performing thermal mitigation includes disconnecting each of the plurality of non-real-time PUs except one of the plurality of non-real-time PUs from the first power supply resulting in an active non-real-time PU, and connecting a second power supply that derives power from the first power supply to the active non-real-time PU, wherein a voltage supplied by the second power supply is less than a voltage supplied by the first power supply.

公开(公告)号：US20200073468A1

公开(公告)日：2020-03-05

申请号：US16674494

申请日：2019-11-05

Applicant: QUALCOMM Incorporated

Inventor： Nikesh Gupta ,  Harshit Tiwari ,  Ashish Bajaj ,  Maheshwar Thakur Singh

IPC: G06F1/3287 ,  G06F1/3296 ,  H04W52/02 ,  G06F1/3234 ,  G06F1/20 ,  G06F1/3206

Abstract: A method of thermal mitigation in a device having a plurality of non-real-time processing units (PUs) and a plurality of real-time PUs, including connecting each of the plurality of real-time PUs and the plurality of non-real-time PUs to a first power supply, and performing thermal mitigation. Performing thermal mitigation includes disconnecting each of the plurality of non-real-time PUs except one of the plurality of non-real-time PUs from the first power supply resulting in an active non-real-time PU, and connecting a second power supply that derives power from the first power supply to the active non-real-time PU, wherein a voltage supplied by the second power supply is less than a voltage supplied by the first power supply.

公开(公告)号：US20160179180A1

公开(公告)日：2016-06-23

申请号：US14579660

申请日：2014-12-22

Applicant: QUALCOMM Incorporated

Inventor： Nikesh Gupta ,  Harshit Tiwari ,  Ashish Bajaj ,  Maheshwar Thakur Singh

IPC: G06F1/32

Abstract: A method of thermal mitigation in a device having a plurality of non-real-time processing units (PUs) and a plurality of real-time PUs, including connecting each of the plurality of real-time PUs and the plurality of non-real-time PUs to a first power supply, and performing thermal mitigation. Performing thermal mitigation includes disconnecting each of the plurality of non-real-time PUs except one of the plurality of non-real-time PUs from the first power supply resulting in an active non-real-time PU, and connecting a second power supply that derives power from the first power supply to the active non-real-time PU, wherein a voltage supplied by the second power supply is less than a voltage supplied by the first power supply.

Abstract translation: 一种具有多个非实时处理单元（PU）和多个实时PU的设备中的热缓解方法，包括连接多个实时PU和多个非实时处理单元 时间PU到第一电源，并执行热减轻。 执行热减轻包括从第一电源断开除了多个非实时PU中的一个以外的多个非实时PU中的每一个，导致活动的非实时PU，并且连接第二电源 其将来自所述第一电源的功率从所述有源非实时PU导出，其中由所述第二电源提供的电压小于由所述第一电源提供的电压。