公开(公告)号：US11507174B2

公开(公告)日：2022-11-22

申请号：US16799936

申请日：2020-02-25

Applicant: QUALCOMM Incorporated

Inventor： Bharat Kumar Rangarajan ,  Srinivas Turaga

IPC: G06F1/3234 ,  G06F1/30 ,  G06F9/4401 ,  G06F12/0895

Abstract: In certain aspects, a tag memory comprises a plurality of non-configurable tag columns configured to be powered on during a normal operation; and a plurality of configurable tag columns, wherein a first portion of the plurality of configurable tag columns is configured to be powered off during the normal operation and a second portion of the plurality of configurable tag columns is configured to be powered on during the normal operation.

公开(公告)号：US12079896B2

公开(公告)日：2024-09-03

申请号：US17736030

申请日：2022-05-03

Applicant: QUALCOMM INCORPORATED

Inventor： Prashant Dinkar Karandikar ,  Pradeep Venkatasubbarao ,  Manmohan Manoharan ,  Vivekanandan Naveen ,  Nagashree Ganapati Upadhya ,  Shubham Sangal ,  Srinivas Turaga ,  Shreya Pandurang Math

IPC: G06T1/20 ,  G06F1/08 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F1/08 ,  G06T1/60

Abstract: In a computing device having a pipeline of image processing components, DCVS bandwidth voting may be based on a feedforward compression ratio determined by the first image processing component in the pipeline. The DCVS bandwidth voting may be based on the result of a comparison of change in the feedforward compression ratio with a threshold. Transaction initiator components in the pipeline may select their votes for bandwidth from among a feedforward compression ratio-based value and one or more other values, based on the result of the comparison with the threshold. DCVS parameters may be selected based on bandwidth votes received from transaction initiator components.

公开(公告)号：US11880454B2

公开(公告)日：2024-01-23

申请号：US16874538

申请日：2020-05-14

Applicant: QUALCOMM Incorporated

Inventor： Bharat Kumar Rangarajan ,  Dipti Ranjan Pal ,  Keith Alan Bowman ,  Srinivas Turaga ,  Ateesh Deepankar De ,  Shih-Hsin Jason Hu ,  Chandan Agarwalla

IPC: G06F21/55 ,  G06F1/26

CPC classification number: G06F21/554 ,  G06F1/26 ,  G06F2221/034

Abstract: A method to prevent a malicious attack on CPU subsystem (CPUSS) hardware is described. The method includes auto-calibrating tunable delay elements of a dynamic variation monitor (DVM) using an auto-calibration value computed in response to each detected change of a clock frequency (Fclk)/supply voltage (Vdd) of the CPUSS hardware. The method also includes comparing the auto-calibration value with a threshold reference calibration value to determine whether the malicious attack is detected. The method further includes forcing a safe clock frequency (Fclk)/safe supply voltage (Vdd) to the CPUSS hardware when the malicious attack is detected.

公开(公告)号：US11630694B2

公开(公告)日：2023-04-18

申请号：US17148314

申请日：2021-01-13

Applicant: QUALCOMM INCORPORATED

Inventor： Vijayakumar Ashok Dibbad ,  Bharat Kumar Rangarajan ,  Prashanth Kumar Kakkireni ,  Srinivas Turaga

IPC: G06F9/46 ,  G06F9/48 ,  G06F1/28 ,  G06F9/52

Abstract: Task scheduling in a computing device may be based in part on voltage regulator efficiency. For an additional task to be scheduled, multiple task scheduling cases may be determined that represent execution of the additional task on each of a number of processors concurrently with one or more other tasks executing among the processors. For each task scheduling case, a regulator input power level for a voltage regulator may be determined based on a performance level indication associated with the additional task, the one or more other tasks executing on the processors, and the efficiency level of each voltage regulator. For each task scheduling case, a total regulator input power level may be determined by summing the regulator input power levels for all voltage regulators. The additional task may be executed on a processor associated with a task scheduling case for which total regulator input power is lowest.

公开(公告)号：US11493986B2

公开(公告)日：2022-11-08

申请号：US16724317

申请日：2019-12-22

Applicant: QUALCOMM Incorporated

Inventor： Bharat Kumar Rangarajan ,  Rajesh Arimilli ,  Srinivas Turaga

IPC: G06F1/00 ,  G06F1/3234 ,  G06F1/3293 ,  G06F1/3296

Abstract: Various embodiments include methods and devices for cache memory power control. Some embodiments may include determining whether a processor is entering a lowest power mode of the processor, and switching a lowest power mode switch control signal to indicate to a cache power switch of the processor switching an electrical connection of a cache memory from a memory power rail to a processor power rail in response to determining that the processor is entering a lowest power mode.

公开(公告)号：US09658671B2

公开(公告)日：2017-05-23

申请号：US15173004

申请日：2016-06-03

Applicant: QUALCOMM Incorporated

Inventor： Harshit Tiwari ,  Akshay Kumar Gupta ,  Srinivas Turaga ,  Deva Sudhir Kumar Pulivendula ,  Venkata Devarasetty

IPC: G11C5/14 ,  G06F1/26 ,  G06F12/0811

CPC classification number: G06F1/266 ,  G06F1/32 ,  G06F12/0811 ,  G06F2212/60 ,  G06F2212/62 ,  G06F2213/0038 ,  G11C5/14

Abstract: A method and an apparatus for providing a power grid are provided. The apparatus includes a plurality of memory units comprising at least one SoC memory and at least one cache memory. The apparatus includes a first subsystem coupled to the at least one SoC memory associated with a first power domain. The apparatus further includes a second subsystem coupled to the at least one cache memory associated with a second power domain. The second subsystem may be a CPU subsystem. Because the first power domain sources power from a shared power source, the first power domain may operate at a voltage level that is higher than the operation of memory circuits requires. By moving the at least one cache memory from the first power domain to the second power domain, LDO efficiency loss for components in the first power domain may be reduced.