Invention Grant
- Patent Title: EDA tool and method for conflict detection during multi-patterning lithography
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Application No.: US14833364Application Date: 2015-08-24
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Publication No.: US09659141B2Publication Date: 2017-05-23
- Inventor: Yen-Hung Lin , Cheng-I Huang , Chin-Chang Hsu , Hung Lung Lin
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing.
Public/Granted literature
- US20150363541A1 EDA TOOL AND METHOD FOR CONFLICT DETECTION DURING MULTI-PATTERNING LITHOGRAPHY Public/Granted day:2015-12-17
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