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公开(公告)号：US09659141B2
公开(公告)日：2017-05-23
申请号：US14833364
申请日：2015-08-24
发明人： Yen-Hung Lin , Cheng-I Huang , Chin-Chang Hsu , Hung Lung Lin
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/06
摘要： A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing.
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公开(公告)号：US09563731B2
公开(公告)日：2017-02-07
申请号：US14210490
申请日：2014-03-14
发明人： Chin-Hsiung Hsu , Li-Chun Tien , Pin-Dai Sue , Ching Hsiang Chang , Wen-Hao Chen , Cheng-I Huang
CPC分类号： G06F17/5068 , G03F1/70 , G03F7/70433 , G03F7/70466
摘要： A system and method of determining a cell layout are disclosed. The method includes receiving a circuit design corresponding to a predetermined circuit design, the circuit design having a first set of cells and abutting adjacent cells in the first set of cells, the abutted cells having a first boundary pattern therebetween. The first boundary pattern is exchanged with a second boundary pattern based on a number or positions of signal wires in the first boundary pattern. A cell layout for use in a patterning process can then be determined, the cell layout including the second boundary pattern.
摘要翻译： 公开了一种确定单元布局的系统和方法。 所述方法包括接收与预定电路设计相对应的电路设计，所述电路设计具有第一组单元并邻接所述第一组单元中的相邻单元，所述邻接单元在其间具有第一边界图案。 基于第一边界图案中的信号线的数量或位置，第一边界图案与第二边界图案交换。 然后可以确定用于图案化处理的单元格布局，单元布局包括第二边界图案。
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3.发明授权EDA tool and method for conflict detection during multi-patterning lithography 有权EDA工具和多图案平版印刷中的冲突检测方法公开(公告)号：US09141752B2
公开(公告)日：2015-09-22
申请号：US14187421
申请日：2014-02-24
发明人： Yen-Hung Lin , Cheng-I Huang , Chin-Chang Hsu , Hung Lung Lin
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/06
摘要： A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing.
摘要翻译： 一种方法包括访问表示具有多个多边形的集成电路（IC）的层的布局的数据，该多个多边形定义要在半导体衬底的单个层上的数个（N个）光掩模中划分的电路图案，其中N较大 比两个。 该方法还包括输入具有多个顶点的冲突图，识别第一和第二顶点，每个顶点连接到第三和第四顶点，其中第三和第四顶点连接到冲突图的相同边缘;以及 合并第一和第二顶点以形成缩小图。 所述方法还包括检测所述缩小的至少一个或多个顶点具有冲突。 在一个方面，该方法通过执行图案移位，针迹插入或重新路由之一来解决检测到的冲突。
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公开(公告)号：US11437321B2
公开(公告)日：2022-09-06
申请号：US16846690
申请日：2020-04-13
发明人： Ni-Wan Fan , Ting-Wei Chiang , Cheng-I Huang , Jung-Chan Yang , Hsiang-Jen Tseng , Lipen Yuan , Chi-Yu Lu
IPC分类号： H01L23/528 , H01L27/02 , H01L27/088 , H01L23/485 , H01L21/8234 , H01L21/768 , H01L23/535 , H01L29/66 , H01L27/118
摘要： The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes first and second source/drain regions within a substrate. A gate structure is over the substrate between the first and second source/drain regions. A middle-end-of-the-line (MEOL) structure is over the second source/drain region. The MEOL structure has a bottommost surface that continuously extends in a first direction from directly contacting a top of the second source/drain region to laterally past an outer edge of the second source/drain region. A conductive structure is on the MEOL structure. A second gate structure is separated from the gate structure by the second source/drain region. The conductive structure continuously extends in a second direction over the MEOL structure and past opposing sides of the second gate structure. A plurality of conductive contacts are configured to electrically couple an interconnect wire and the MEOL structure along through the conductive structure.
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公开(公告)号：US11294286B2
公开(公告)日：2022-04-05
申请号：US16287450
申请日：2019-02-27
发明人： Ru-Gun Liu , Chin-Hsiang Lin , Cheng-I Huang , Chih-Ming Lai , Chien-Wen Lai , Ken-Hsien Hsieh , Shih-Ming Chang , Yuan-Te Hou
摘要： A photo mask for manufacturing a semiconductor device includes a first pattern extending in a first direction, a second pattern extending in the first direction and aligned with the first pattern, and a sub-resolution pattern extending in the first direction, disposed between an end of the first pattern and an end of the second pattern. A width of the first pattern and a width of the second pattern are equal to each other, and the first pattern and the second pattern are for separate circuit elements in the semiconductor device.
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公开(公告)号：US20180350743A1
公开(公告)日：2018-12-06
申请号：US16057875
申请日：2018-08-08
发明人： Ni-Wan Fan , Ting-Wei Chiang , Cheng-I Huang , Jung-Chan Yang , Hsiang-Jen Tseng , Lipen Yuan , Chi-Yu Lu
IPC分类号： H01L23/528 , H01L29/66 , H01L27/02 , H01L21/768 , H01L27/088 , H01L23/535 , H01L21/8234 , H01L27/118
CPC分类号： H01L23/5286 , H01L21/76805 , H01L21/76816 , H01L21/76895 , H01L21/823475 , H01L23/535 , H01L27/0207 , H01L27/088 , H01L27/0886 , H01L27/11807 , H01L29/66545
摘要： The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method is performed by forming a gate structure over a substrate, and selectively implanting the substrate according to the gate structure to form first and second source/drain regions on opposing sides of the gate structure. A first MEOL structure is formed on the first source/drain region and a second MEOL structure is formed on the second source/drain region. The first MEOL structure has a bottommost surface that extends in a first direction from directly over the first source/drain region to laterally past an outermost edge of the first source/drain region. A conductive structure is formed to contact the first MEOL structure and the second MEOL structure. The conductive structure laterally extends from directly over the first MEOL structure to directly over the second MEOL structure along a second direction perpendicular to the first direction.
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公开(公告)号：US09262558B2
公开(公告)日：2016-02-16
申请号：US13867154
申请日：2013-04-22
发明人： Cheng-I Huang , Hsiao-Shu Chao , Yi-kan Cheng
CPC分类号： G06F17/50 , G03F1/36 , G03F1/38 , G06F17/5081 , G06F2217/84 , H01L27/0207
摘要： A method includes performing a place and route operation using an electronic design automation tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device. The place and route operation is constrained by a plurality of single patterning spacer technique (SPST) routing rules. Dummy conductive fill patterns are emulated within the EDA tool using an RC extraction tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask. An RC timing analysis of the circuit pattern is performed within the EDA tool, based on the preliminary layout and the emulated dummy conductive fill patterns.
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公开(公告)号：US10672708B2
公开(公告)日：2020-06-02
申请号：US15170246
申请日：2016-06-01
发明人： Ni-Wan Fan , Ting-Wei Chiang , Cheng-I Huang , Jung-Chan Yang , Hsiang-Jen Tseng , Lipen Yuan , Chi-Yu Lu
IPC分类号： H01L23/528 , H01L27/088 , H01L23/485 , H01L21/768 , H01L23/535 , H01L29/66 , H01L27/02 , H01L21/8234 , H01L27/118
摘要： In some embodiments, the present disclosure relates to an integrated circuit (IC) having parallel conductive paths between a BEOL interconnect layer and a middle-end-of-the-line (MEOL) structure, which are configured to reduce a parasitic resistance and/or capacitance of the IC. The IC comprises source/drain regions arranged within a substrate and separated by a channel region. A gate structure is arranged over the channel region and a MEOL structure is arranged over one of the source/drain regions. A conductive structure is arranged over and in electrical contact with the MEOL structure. A first conductive contact is arranged between the MEOL structure and an overlying BEOL interconnect wire (e.g., a power rail). A second conductive contact is configured to electrically couple the BEOL interconnect wire and the MEOL structure along a conductive path extending through the conductive structure, thereby forming parallel conductive paths between the BEOL interconnect layer and the MEOL structure.
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公开(公告)号：US20170154848A1
公开(公告)日：2017-06-01
申请号：US15170246
申请日：2016-06-01
发明人： Ni-Wan Fan , Ting-Wei Chiang , Cheng-I Huang , Jung-Chan Yang , Hsiang-Jen Tseng , Lipen Yuan , Chi-Yu Lu
IPC分类号： H01L23/528 , H01L29/66 , H01L27/088 , H01L23/535 , H01L21/768
摘要： In some embodiments, the present disclosure relates to an integrated circuit (IC) having parallel conductive paths between a BEOL interconnect layer and a middle-end-of-the-line (MEOL) structure, which are configured to reduce a parasitic resistance and/or capacitance of the IC. The IC comprises source/drain regions arranged within a substrate and separated by a channel region. A gate structure is arranged over the channel region and a MEOL structure is arranged over one of the source/drain regions. A conductive structure is arranged over and in electrical contact with the MEOL structure. A first conductive contact is arranged between the MEOL structure and an overlying BEOL interconnect wire (e.g., a power rail). A second conductive contact is configured to electrically couple the BEOL interconnect wire and the MEOL structure along a conductive path extending through the conductive structure, thereby forming parallel conductive paths between the BEOL interconnect layer and the MEOL structure.
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公开(公告)号：US12125839B2
公开(公告)日：2024-10-22
申请号：US17107311
申请日：2020-11-30
IPC分类号： H01L27/02 , G06F30/39 , H01L21/8234 , H01L27/088 , H01L29/66
CPC分类号： H01L27/0207 , G06F30/39 , H01L27/0886 , H01L29/66545 , H01L21/823431
摘要： A semiconductor device includes a first fin, a first continuous fin and continuous gates. The first fin is formed on a substrate, and includes first and second portions that are spaced apart by a first recess. A side of the first portion and a side of the second portion are located at two sides of the first recess, respectively. The first continuous fin is formed on the substrate, and extends along the first portion, the first recess and the second portion. The continuous gates are formed on the substrate, and arranged to intersect the first continuous fin and the first fin in a layout view. A first number of the continuous gates are disposed across the first recess and each of the first number of the continuous gates is disposed between the two sides of the first recess in a layout view. A method is also disclosed herein.
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