公开(公告)号：US09471744B2

公开(公告)日：2016-10-18

申请号：US14819590

申请日：2015-08-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung Lung Lin ,  Chin-Chang Hsu ,  Min-Yuan Tsai ,  Wen-Ju Yang ,  Chien Lin Ho

IPC: G06F17/50 ,  G03F7/00

CPC classification number: G06F17/5081 ,  G03F7/0035 ,  G06F17/509

Abstract: Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium.

公开(公告)号：US09026971B1

公开(公告)日：2015-05-05

申请号：US14148898

申请日：2014-01-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Lin Ho ,  Chin-Chang Hsu ,  Hung Lung Lin ,  Wen-Ju Yang ,  Yi-Kan Cheng ,  Tsong-Hua Ou ,  Wen-Li Cheng ,  Ken-Hsien Hsieh ,  Ching Hsiang Chang ,  Ting Yu Chen ,  Li-Chun Tien

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F7/70466 ,  G06F17/5072 ,  G06F2217/12 ,  Y02P90/265

Abstract: The present disclosure relates to a method and apparatus for forming a multiple patterning lithograph (MPL) compliant integrated circuit layout by operating a construction validation check on unassembled IC cells to enforce design restrictions that prevent MPL conflicts after assembly. In some embodiments, the method is performed by generating a plurality of unassembled integrated circuit (IC) cells having a multiple patterning design layer. A construction validation check is performed on the unassembled IC cells to identify violating IC cells having shapes disposed in patterns comprising potential multiple patterning coloring conflicts. Design shapes within a violating IC cell are adjusted to achieve a plurality of violation free IC cells. The plurality of violation free IC cells are then assembled to form an MPL compliant IC layout. Since the MPL compliant IC layout is free of coloring conflicts, a decomposition algorithm can be operated without performing a post assembly color conflict check.

Abstract translation: 本发明涉及一种用于通过对未组装的IC单元进行构造验证检查以形成在组装之后防止MPL冲突的设计限制来形成多重图案化平版印刷术（MPL）兼容集成电路布局的方法和装置。 在一些实施例中，该方法通过产生具有多个图案化设计层的多个未组装的集成电路（IC）单元来执行。 在未组装的IC细胞上进行结构验证检查，以识别具有以包含潜在的多个图案化着色冲突的图案布置的形状的违反IC细胞。 调整违规IC单元内的设计形状，以实现多个无冲突的IC单元。 然后组合多个违规免费IC电池以形成符合MPL的IC布局。 由于MPL兼容IC布局没有着色冲突，因此可以在不执行后期组合颜色冲突检查的情况下操作分解算法。

公开(公告)号：US09659141B2

公开(公告)日：2017-05-23

申请号：US14833364

申请日：2015-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung Lin ,  Cheng-I Huang ,  Chin-Chang Hsu ,  Hung Lung Lin

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/06

Abstract: A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing.

公开(公告)号：US09141752B2

公开(公告)日：2015-09-22

申请号：US14187421

申请日：2014-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung Lin ,  Cheng-I Huang ,  Chin-Chang Hsu ,  Hung Lung Lin

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/06

Abstract: A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing.

Abstract translation: 一种方法包括访问表示具有多个多边形的集成电路（IC）的层的布局的数据，该多个多边形定义要在半导体衬底的单个层上的数个（N个）光掩模中划分的电路图案，其中N较大 比两个。 该方法还包括输入具有多个顶点的冲突图，识别第一和第二顶点，每个顶点连接到第三和第四顶点，其中第三和第四顶点连接到冲突图的相同边缘;以及 合并第一和第二顶点以形成缩小图。 所述方法还包括检测所述缩小的至少一个或多个顶点具有冲突。 在一个方面，该方法通过执行图案移位，针迹插入或重新路由之一来解决检测到的冲突。

公开(公告)号：US09122838B2

公开(公告)日：2015-09-01

申请号：US14302684

申请日：2014-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung Lung Lin ,  Chin-Chang Hsu ,  Min-Yuan Tsai ,  Wen-Ju Yang ,  Chien Lin Ho

IPC: G06F17/50 ,  G03F7/00

CPC classification number: G06F17/5081 ,  G03F7/0035 ,  G06F17/509

Abstract: Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium.

Abstract translation: 提供了一种用于在半导体制造中评估和分解用于三重图案光刻的半导体器件电平的方法。 该方法包括使用各种方法生成冲突图并简化冲突图，以产生可以进一步简化或评估分解有效性的简化冲突图。 本公开还提供将分解有效性规则应用于简化的冲突图，以确定冲突图是否表示可分解成三个掩模的半导体器件层。 公开的方法由计算机执行，并且用于执行该方法的指令可以存储在计算机可读存储介质上。

公开(公告)号：US08875065B1

公开(公告)日：2014-10-28

申请号：US13953767

申请日：2013-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung Lung Lin ,  Chin-Chang Hsu ,  Min-Yuan Tsai ,  Wen-Ju Yang

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/509

Abstract: A method of decomposing a layout for triple pattern lithography generates a first conflict graph from the layout. The method generates a second conflict graph from the first conflict graph, and identifies loops in the second conflict graph as decomposition violations.

Abstract translation: 分解三重图案光刻的布局的方法从布局生成第一冲突图。 该方法从第一冲突图生成第二冲突图，并将第二冲突图中的循环识别为分解违规。