Invention Grant
- Patent Title: Wafer-level flipped die stacks with leadframes or metal foil interconnects
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Application No.: US15342744Application Date: 2016-11-03
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Publication No.: US09666513B2Publication Date: 2017-05-30
- Inventor: Ashok S. Prabhu , Rajesh Katkar , Sean Moran
- Applicant: Invensas Corporation
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Agency: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- Main IPC: H01L23/552
- IPC: H01L23/552 ; H01L23/495 ; H01L23/29 ; H01L23/31 ; H01L21/56 ; H01L25/10 ; H01L25/00 ; H01L23/00

Abstract:
An assembly includes a plurality of stacked encapsulated microelectronic packages, each package including a microelectronic element having a front surface with a plurality of chip contacts at the front surface and edge surfaces extending away from the front surface. An encapsulation region of each package contacts at least one edge surface and extends away therefrom to a remote surface of the package. The package contacts of each package are disposed at a single one of the remote surfaces, the package contacts facing and coupled with corresponding contacts at a surface of a substrate nonparallel with the front surfaces of the microelectronic elements therein.
Public/Granted literature
- US20170077016A1 WAFER-LEVEL FLIPPED DIE STACKS WITH LEADFRAMES OR METAL FOIL INTERCONNECTS Public/Granted day:2017-03-16
Information query
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