Invention Grant
- Patent Title: Isolation scheme for high voltage device
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Application No.: US14958873Application Date: 2015-12-03
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Publication No.: US09673084B2Publication Date: 2017-06-06
- Inventor: Kun Liu , Francis Benistant , Ming Li , Namchil Mun , Shiang Yang Ong , Purakh Raj Verma
- Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Current Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Current Assignee Address: SG Singapore
- Agency: Horizon IP Pte. Ltd.
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L21/763 ; H01L29/06 ; H01L29/78

Abstract:
Semiconductor device isolation and method of forming thereof are presented. A base substrate with lightly doped first polarity type dopants is provided. A buried layer with heavily doped second polarity type dopants is formed in a top portion of the substrate while an epitaxial layer is formed over the buried layer. First and second type deep trench isolation (DTI) structures which extend from surface of the epitaxial layer to a portion of the base substrate are formed to isolate different device regions defined in the substrate. The first and second type DTI structures have different width dimensions. Shallow trench isolation (STI) regions are formed in the epitaxial layer and at least one transistor is formed on the epitaxial layer. The first and second type DTI structures effectively isolate the transistor from other device regions and enhances the breakdown voltage.
Public/Granted literature
- US20160163583A1 ISOLATION SCHEME FOR HIGH VOLTAGE DEVICE Public/Granted day:2016-06-09
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