公开(公告)号：US09871132B1

公开(公告)日：2018-01-16

申请号：US15236494

申请日：2016-08-15

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Kun Liu ,  Xiaoping Wang ,  Francis Lionel Benistant ,  Li Cao

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L21/768 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L21/76897 ,  H01L29/402 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: Devices and methods for forming a device are disclosed. A transistor is formed on the substrate. The transistor includes a gate, a source and a drain. An insulation layer is formed on the substrate. The insulation layer is partially disposed on the gate and a sidewall of the gate. The drain is offset from the gate by the insulation layer. An overlayer is formed on the substrate covering the transistor and insulation layer. A field plate in the form of a field plate contact is formed in the overlayer. The field plate contact is disposed on and coupled to the insulation layer for mitigating the formation of electric field adjacent to drain side of the gate.

公开(公告)号：US09673084B2

公开(公告)日：2017-06-06

申请号：US14958873

申请日：2015-12-03

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Kun Liu ,  Francis Benistant ,  Ming Li ,  Namchil Mun ,  Shiang Yang Ong ,  Purakh Raj Verma

IPC: H01L21/762 ,  H01L21/763 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L21/76229 ,  H01L21/76283 ,  H01L21/763 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/66681 ,  H01L29/78 ,  H01L29/7816

Abstract: Semiconductor device isolation and method of forming thereof are presented. A base substrate with lightly doped first polarity type dopants is provided. A buried layer with heavily doped second polarity type dopants is formed in a top portion of the substrate while an epitaxial layer is formed over the buried layer. First and second type deep trench isolation (DTI) structures which extend from surface of the epitaxial layer to a portion of the base substrate are formed to isolate different device regions defined in the substrate. The first and second type DTI structures have different width dimensions. Shallow trench isolation (STI) regions are formed in the epitaxial layer and at least one transistor is formed on the epitaxial layer. The first and second type DTI structures effectively isolate the transistor from other device regions and enhances the breakdown voltage.

公开(公告)号：US11996441B2

公开(公告)日：2024-05-28

申请号：US17547288

申请日：2021-12-10

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Bong Woong Mun ,  Kun Liu

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0607 ,  H01L21/76202 ,  H01L21/76224 ,  H01L29/66712 ,  H01L29/7802

Abstract: A device includes a first region disposed on a substrate, a second region disposed on the first region, a third region disposed in the second region and a first terminal region disposed in the third region. The first region comprises a discontinuous layer including at least one gap portion. The at least one gap portion comprises a portion of the substrate. The first region and the second region have a first conductivity type, and the substrate, the third region and the first terminal region have a second conductivity type. The first conductivity type is different from the second conductivity type.