- 专利标题： Disabling cache portions during low voltage operations
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申请号： US13652480申请日： 2012-10-16
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公开(公告)号： US09678878B2公开(公告)日： 2017-06-13
- 发明人: Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
- 申请人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Mnemoglyphics, LLC
- 代理商 Lawrence M. Mennemeier
- 主分类号： G06F12/08
- IPC分类号： G06F12/08 ; G06F12/126 ; G06F12/0864 ; G06F12/0804 ; G06F1/32
摘要：
Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
公开/授权文献
- US20140108733A1 DISABLING CACHE PORTIONS DURING LOW VOLTAGE OPERATIONS 公开/授权日：2014-04-17
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