Invention Grant
- Patent Title: Satisfying memory ordering requirements between partial reads and non-snoop accesses
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Application No.: US14583596Application Date: 2014-12-27
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Publication No.: US09703712B2Publication Date: 2017-07-11
- Inventor: Robert H. Beers , Ching-Tsun Chou , Robert J. Safranek , James Vash
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Patent Capital Group
- Main IPC: G06F12/14
- IPC: G06F12/14 ; G06F12/0831 ; H04L29/08 ; G06F12/0817 ; G06F12/0806 ; G06F12/128 ; G06F12/0813

Abstract:
A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data.
Public/Granted literature
- US20150178210A1 SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND NON-SNOOP ACCESSES Public/Granted day:2015-06-25
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