公开(公告)号：US09703712B2

公开(公告)日：2017-07-11

申请号：US14583596

申请日：2014-12-27

Applicant: Intel Corporation

Inventor： Robert H. Beers ,  Ching-Tsun Chou ,  Robert J. Safranek ,  James Vash

IPC: G06F12/14 ,  G06F12/0831 ,  H04L29/08 ,  G06F12/0817 ,  G06F12/0806 ,  G06F12/128 ,  G06F12/0813

CPC classification number: G06F12/0833 ,  G06F12/0806 ,  G06F12/0813 ,  G06F12/0824 ,  G06F12/0831 ,  G06F12/128 ,  G06F2212/2542 ,  G06F2212/62 ,  G06F2212/621 ,  G06F2212/69 ,  G06F2212/70 ,  H04L67/28 ,  H04L67/2842

Abstract: A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data.

公开(公告)号：US20170351516A1

公开(公告)日：2017-12-07

申请号：US15175899

申请日：2016-06-07

Applicant: Intel Corporation

Inventor： Vineeth Mekkat ,  Oleg Margulis ,  Ching-Tsun Chou ,  Youfeng Wu

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/32 ,  G06F12/0831 ,  G06F12/0875

CPC classification number: G06F9/30043 ,  G06F9/3017 ,  G06F9/327 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3855

Abstract: A processor includes a front end including circuitry to decode instructions from an instruction stream, a data cache unit including circuitry to cache data for the processor, and a binary translator. The binary translator includes circuitry to identify a redundant store in the instruction stream, mark the start and end of a region of the instruction stream with the redundant store, remove the redundant store, and store an amended instruction stream with the redundant store removed.

公开(公告)号：US10761849B2

公开(公告)日：2020-09-01

申请号：US15273163

申请日：2016-09-22

Applicant: Intel Corporation

Inventor： Ching-Tsun Chou ,  Oleg Margulis ,  Tyler N. Sondag

IPC: G06F9/30

Abstract: A processor of an aspect includes a decode unit to decode a prior instruction that is to have at least a first context, and a subsequent instruction. The subsequent instruction is to be after the prior instruction in original program order. The decode unit is to use the first context of the prior instruction to determine a second context for the subsequent instruction. The processor also includes an execution unit coupled with the decode unit. The execution unit is to perform the subsequent instruction based at least in part on the second context. Other processors, methods, systems, and machine-readable medium are also disclosed.

公开(公告)号：US10019366B2

公开(公告)日：2018-07-10

申请号：US15646961

申请日：2017-07-11

Applicant: Intel Corporation

Inventor： Robert H. Beers ,  Ching-Tsun Chou ,  Robert J. Safranek ,  James Vash

IPC: G06F12/00 ,  G06F12/0831 ,  H04L29/08 ,  G06F12/0817 ,  G06F12/0806 ,  G06F12/128 ,  G06F12/0813

CPC classification number: G06F12/0833 ,  G06F12/0806 ,  G06F12/0813 ,  G06F12/0824 ,  G06F12/0831 ,  G06F12/12 ,  G06F12/128 ,  G06F2212/2542 ,  G06F2212/62 ,  G06F2212/621 ,  G06F2212/70 ,  H04L67/28 ,  H04L67/2842

Abstract: A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data.

公开(公告)号：US09058271B2

公开(公告)日：2015-06-16

申请号：US14142827

申请日：2013-12-28

Applicant: Intel Corporation

Inventor： Robert H. Beers ,  Ching-Tsun Chou ,  Robert J. Safranek ,  James Vash

IPC: G06F13/16 ,  G06F12/08 ,  H04L29/08

CPC classification number: G06F12/0833 ,  G06F12/0806 ,  G06F12/0813 ,  G06F12/0824 ,  G06F12/0831 ,  G06F12/128 ,  G06F2212/2542 ,  G06F2212/62 ,  G06F2212/621 ,  G06F2212/69 ,  G06F2212/70 ,  H04L67/28 ,  H04L67/2842

Abstract: A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data.

Abstract translation: 这里描述了一种基于部分和非相干存储器访问的基于高速缓存基于相干链路的互连中的存储器排序的方法和装置。 在一个实施例中，使用Read Invalidate和/或Snoop Invalidate消息来实现部分存储器访问，诸如部分读取。 当对等节点接收到从请求节点引用数据的Snoop Invalidate消息时，对等节点将使与数据相关联的高速缓存行无效，并且不将数据直接转发到请求节点。 在一个实施例中，当对等节点保持被修改的一致性状态下的被引用高速缓存行时，响应于接收到无效无效消息，对等节点将该数据写回到与该数据相关联的家庭节点。

公开(公告)号：US10120686B2

公开(公告)日：2018-11-06

申请号：US15175899

申请日：2016-06-07

Applicant: Intel Corporation

Inventor： Vineeth Mekkat ,  Oleg Margulis ,  Ching-Tsun Chou ,  Youfeng Wu

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32

Abstract: A processor includes a front end including circuitry to decode instructions from an instruction stream, a data cache unit including circuitry to cache data for the processor, and a binary translator. The binary translator includes circuitry to identify a redundant store in the instruction stream, mark the start and end of a region of the instruction stream with the redundant store, remove the redundant store, and store an amended instruction stream with the redundant store removed.

公开(公告)号：US20180081684A1

公开(公告)日：2018-03-22

申请号：US15273163

申请日：2016-09-22

Applicant: Intel Corporation

Inventor： Ching-Tsun Chou ,  Oleg Margulis ,  Tyler N. Sondag

IPC: G06F9/30

Abstract: A processor of an aspect includes a decode unit to decode a prior instruction that is to have at least a first context, and a subsequent instruction. The subsequent instruction is to be after the prior instruction in original program order. The decode unit is to use the first context of the prior instruction to determine a second context for the subsequent instruction. The processor also includes an execution unit coupled with the decode unit. The execution unit is to perform the subsequent instruction based at least in part on the second context. Other processors, methods, systems, and machine-readable medium are also disclosed.