公开(公告)号：US20150178210A1

公开(公告)日：2015-06-25

申请号：US14583596

申请日：2014-12-27

申请人： Intel Corporation

发明人： Robert H. Beers ,  Ching- Tsun Chou ,  Robert J. Safranek ,  James Vash

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F12/0833 ,  G06F12/0806 ,  G06F12/0813 ,  G06F12/0824 ,  G06F12/0831 ,  G06F12/128 ,  G06F2212/2542 ,  G06F2212/62 ,  G06F2212/621 ,  G06F2212/69 ,  G06F2212/70 ,  H04L67/28 ,  H04L67/2842

摘要： A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data.

摘要翻译： 这里描述了一种基于部分和非相干存储器访问的基于高速缓存基于相干链路的互连中的存储器排序的方法和装置。 在一个实施例中，使用Read Invalidate和/或Snoop Invalidate消息来实现部分存储器访问，诸如部分读取。 当对等节点接收到从请求节点引用数据的Snoop Invalidate消息时，对等节点将使与数据相关联的高速缓存行无效，并且不将数据直接转发到请求节点。 在一个实施例中，当对等节点保持被修改的一致性状态下的被引用高速缓存行时，响应于接收到无效无效消息，对等节点将该数据写回到与该数据相关联的家庭节点。

公开(公告)号：US10248591B2

公开(公告)日：2019-04-02

申请号：US15393153

申请日：2016-12-28

申请人： Intel Corporation

发明人： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert H. Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC分类号： G06F13/22 ,  G06F12/0831 ,  G06F13/42 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30 ,  G06F12/0806 ,  H04L12/933 ,  G06F9/46 ,  G06F13/40 ,  G06F12/0813 ,  G06F12/0815 ,  G06F9/445 ,  G06F1/3287 ,  G06F11/10 ,  H04L9/06 ,  G06F12/0808 ,  H04L12/741 ,  G06F8/73 ,  H04L12/46

摘要： A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

公开(公告)号：US09703712B2

公开(公告)日：2017-07-11

申请号：US14583596

申请日：2014-12-27

申请人： Intel Corporation

发明人： Robert H. Beers ,  Ching-Tsun Chou ,  Robert J. Safranek ,  James Vash

IPC分类号： G06F12/14 ,  G06F12/0831 ,  H04L29/08 ,  G06F12/0817 ,  G06F12/0806 ,  G06F12/128 ,  G06F12/0813

CPC分类号： G06F12/0833 ,  G06F12/0806 ,  G06F12/0813 ,  G06F12/0824 ,  G06F12/0831 ,  G06F12/128 ,  G06F2212/2542 ,  G06F2212/62 ,  G06F2212/621 ,  G06F2212/69 ,  G06F2212/70 ,  H04L67/28 ,  H04L67/2842

摘要： A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data.

公开(公告)号：US20170109286A1

公开(公告)日：2017-04-20

申请号：US15393577

申请日：2016-12-29

申请人： Intel Corporation

发明人： Robert G. Blankenship ,  Bahaa Fahim ,  Robert H. Beers ,  Yen-Cheng Liu ,  Vedaraman Geetha ,  Herbert H. Hum ,  Jeff Willey

IPC分类号： G06F12/0831 ,  G06F12/0808

CPC分类号： G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/73 ,  G06F8/77 ,  G06F9/30145 ,  G06F9/44505 ,  G06F9/466 ,  G06F11/1004 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4273 ,  G06F13/4282 ,  G06F13/4286 ,  G06F13/4291 ,  G06F2212/1016 ,  G06F2212/2542 ,  G06F2212/622 ,  H04L9/0662 ,  H04L12/4641 ,  H04L45/74 ,  H04L49/15 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/40 ,  Y02D10/44 ,  Y02D30/30

摘要： A request is received that is to reference a first agent and to request a particular line of memory to be cached in an exclusive state. A snoop request is sent intended for one or more other agents. A snoop response is received that is to reference a second agent, the snoop response to include a writeback to memory of a modified cache line that is to correspond to the particular line of memory. A complete is sent to be addressed to the first agent, wherein the complete is to include data of the particular line of memory based on the writeback.

公开(公告)号：US10019366B2

公开(公告)日：2018-07-10

申请号：US15646961

申请日：2017-07-11

申请人： Intel Corporation

发明人： Robert H. Beers ,  Ching-Tsun Chou ,  Robert J. Safranek ,  James Vash

IPC分类号： G06F12/00 ,  G06F12/0831 ,  H04L29/08 ,  G06F12/0817 ,  G06F12/0806 ,  G06F12/128 ,  G06F12/0813

CPC分类号： G06F12/0833 ,  G06F12/0806 ,  G06F12/0813 ,  G06F12/0824 ,  G06F12/0831 ,  G06F12/12 ,  G06F12/128 ,  G06F2212/2542 ,  G06F2212/62 ,  G06F2212/621 ,  G06F2212/70 ,  H04L67/28 ,  H04L67/2842

摘要： A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data.

公开(公告)号：US20170308471A1

公开(公告)日：2017-10-26

申请号：US15646961

申请日：2017-07-11

申请人： Intel Corporation

发明人： Robert H. Beers ,  Ching- Tsun Chou ,  Robert J. Safranek ,  James Vash

IPC分类号： G06F12/0831 ,  G06F12/0817 ,  H04L29/08 ,  G06F12/0806 ,  G06F12/128 ,  G06F12/0813

CPC分类号： G06F12/0833 ,  G06F12/0806 ,  G06F12/0813 ,  G06F12/0824 ,  G06F12/0831 ,  G06F12/128 ,  G06F2212/2542 ,  G06F2212/62 ,  G06F2212/621 ,  G06F2212/69 ,  G06F2212/70 ,  H04L67/28 ,  H04L67/2842

摘要： A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data.

公开(公告)号：US20170109315A1

公开(公告)日：2017-04-20

申请号：US15393153

申请日：2016-12-28

申请人： Intel Corporation

发明人： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert H. Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC分类号： G06F13/42 ,  H04L9/06 ,  G06F11/10 ,  G06F13/40

CPC分类号： G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/73 ,  G06F8/77 ,  G06F9/30145 ,  G06F9/44505 ,  G06F9/466 ,  G06F11/1004 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4273 ,  G06F13/4282 ,  G06F13/4286 ,  G06F13/4291 ,  G06F2212/1016 ,  G06F2212/2542 ,  G06F2212/622 ,  H04L9/0662 ,  H04L12/4641 ,  H04L45/74 ,  H04L49/15 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/40 ,  Y02D10/44 ,  Y02D30/30

摘要： A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

公开(公告)号：US09058271B2

公开(公告)日：2015-06-16

申请号：US14142827

申请日：2013-12-28

申请人： Intel Corporation

发明人： Robert H. Beers ,  Ching-Tsun Chou ,  Robert J. Safranek ,  James Vash

IPC分类号： G06F13/16 ,  G06F12/08 ,  H04L29/08

CPC分类号： G06F12/0833 ,  G06F12/0806 ,  G06F12/0813 ,  G06F12/0824 ,  G06F12/0831 ,  G06F12/128 ,  G06F2212/2542 ,  G06F2212/62 ,  G06F2212/621 ,  G06F2212/69 ,  G06F2212/70 ,  H04L67/28 ,  H04L67/2842

摘要： A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data.

摘要翻译： 这里描述了一种基于部分和非相干存储器访问的基于高速缓存基于相干链路的互连中的存储器排序的方法和装置。 在一个实施例中，使用Read Invalidate和/或Snoop Invalidate消息来实现部分存储器访问，诸如部分读取。 当对等节点接收到从请求节点引用数据的Snoop Invalidate消息时，对等节点将使与数据相关联的高速缓存行无效，并且不将数据直接转发到请求节点。 在一个实施例中，当对等节点保持被修改的一致性状态下的被引用高速缓存行时，响应于接收到无效无效消息，对等节点将该数据写回到与该数据相关联的家庭节点。