Invention Grant
- Patent Title: On-chip impedance network with digital coarse and analog fine tuning
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Application No.: US14829511Application Date: 2015-08-18
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Publication No.: US09705497B2Publication Date: 2017-07-11
- Inventor: Curtis Dicke , George Courville , David Fisch , Randall Sandusky , Kent Stalnaker
- Applicant: Invensas Corporation
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: H03L5/00
- IPC: H03L5/00 ; H03K19/00 ; H01C10/50 ; G11C7/10 ; H03F3/45

Abstract:
System and method for providing precision a self calibrating resistance circuit is described that provides for matching a reference resistor using dynamically configurable resistance networks. The resistor network is coupled to the connection, wherein the resistor network provides a configurable resistance across the connection. In addition, the resistor network comprises a digital resistor network and an analog resistor network. Also, the circuit includes control circuitry for configuring the configurable resistance based on a reference resistance of the reference resistor. The configurable resistance is configured by coarsely tuning the resistor network through the digital resistor network and fine tuning the resistor network through the analog resistor network.
Public/Granted literature
- US20160094223A1 ON-CHIP IMPEDANCE NETWORK WITH DIGITAL COARSE AND ANALOG FINE TUNING Public/Granted day:2016-03-31
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