公开(公告)号：US20160189765A1

公开(公告)日：2016-06-30

申请号：US15065378

申请日：2016-03-09

Applicant: Invensas Corporation

Inventor： David Edward Fisch ,  William C. Plants ,  Kent Stalnaker

IPC: G11C11/4091 ,  G11C11/408

CPC classification number: G11C11/4091 ,  G11C7/00 ,  G11C7/02 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1069 ,  G11C7/1096 ,  G11C11/4087 ,  G11C11/4096 ,  G11C29/52

Abstract: A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.

公开(公告)号：US09705497B2

公开(公告)日：2017-07-11

申请号：US14829511

申请日：2015-08-18

Applicant: Invensas Corporation

Inventor： Curtis Dicke ,  George Courville ,  David Fisch ,  Randall Sandusky ,  Kent Stalnaker

IPC: H03L5/00 ,  H03K19/00 ,  H01C10/50 ,  G11C7/10 ,  H03F3/45

CPC classification number: H03K19/0005 ,  G11C7/1057 ,  H01C10/50 ,  H03F3/45475

Abstract: System and method for providing precision a self calibrating resistance circuit is described that provides for matching a reference resistor using dynamically configurable resistance networks. The resistor network is coupled to the connection, wherein the resistor network provides a configurable resistance across the connection. In addition, the resistor network comprises a digital resistor network and an analog resistor network. Also, the circuit includes control circuitry for configuring the configurable resistance based on a reference resistance of the reference resistor. The configurable resistance is configured by coarsely tuning the resistor network through the digital resistor network and fine tuning the resistor network through the analog resistor network.

公开(公告)号：US20170310322A1

公开(公告)日：2017-10-26

申请号：US15645125

申请日：2017-07-10

Applicant: Invensas Corporation

Inventor： Curtis Dicke ,  George Courville ,  David Edward Fisch ,  Randall Sandusky ,  Kent Stalnaker

IPC: H03K19/00 ,  G11C7/10 ,  H01C10/50 ,  H03F3/45

CPC classification number: H03K19/0005 ,  G11C7/1057 ,  H01C10/50 ,  H03F3/45475

Abstract: System and method for providing precision a self calibrating resistance circuit is described that provides for matching a reference resistor using dynamically configurable resistance networks. The resistor network is coupled to the connection, wherein the resistor network provides a configurable resistance across the connection. In addition, the resistor network comprises a digital resistor network and an analog resistor network. Also, the circuit includes control circuitry for configuring the configurable resistance based on a reference resistance of the reference resistor. The configurable resistance is configured by coarsely tuning the resistor network through the digital resistor network and fine tuning the resistor network through the analog resistor network.

公开(公告)号：US09007866B2

公开(公告)日：2015-04-14

申请号：US13868884

申请日：2013-04-23

Applicant: Invensas Corporation

Inventor： David Edward Fisch ,  William C. Plants ,  Kent Stalnaker

IPC: G11C5/14 ,  G11C29/52 ,  G11C7/02 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/06 ,  G11C11/4091

CPC classification number: G11C11/4091 ,  G11C7/00 ,  G11C7/02 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1069 ,  G11C7/1096 ,  G11C11/4087 ,  G11C11/4096 ,  G11C29/52

Abstract: A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.

公开(公告)号：US10164633B2

公开(公告)日：2018-12-25

申请号：US15645125

申请日：2017-07-10

Applicant: Invensas Corporation

Inventor： Curtis Dicke ,  George Courville ,  David Edward Fisch ,  Randall Sandusky ,  Kent Stalnaker

IPC: H03L5/00 ,  H03K19/00 ,  H01C10/50 ,  G11C7/10 ,  H03F3/45

Abstract: System and method for providing precision a self calibrating resistance circuit is described that provides for matching a reference resistor using dynamically configurable resistance networks. The resistor network is coupled to the connection, wherein the resistor network provides a configurable resistance across the connection. In addition, the resistor network comprises a digital resistor network and an analog resistor network. Also, the circuit includes control circuitry for configuring the configurable resistance based on a reference resistance of the reference resistor. The configurable resistance is configured by coarsely tuning the resistor network through the digital resistor network and fine tuning the resistor network through the analog resistor network.

公开(公告)号：US09299398B2

公开(公告)日：2016-03-29

申请号：US14683687

申请日：2015-04-10

Applicant: Invensas Corporation

Inventor： David Edward Fisch ,  William C. Plants ,  Kent Stalnaker

IPC: G11C5/14 ,  G11C7/00 ,  G11C29/52 ,  G11C7/02 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/06 ,  G11C11/4091

CPC classification number: G11C11/4091 ,  G11C7/00 ,  G11C7/02 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1069 ,  G11C7/1096 ,  G11C11/4087 ,  G11C11/4096 ,  G11C29/52

Abstract: A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.

公开(公告)号：US09548101B2

公开(公告)日：2017-01-17

申请号：US15065378

申请日：2016-03-09

Applicant: Invensas Corporation

Inventor： David Edward Fisch ,  William C. Plants ,  Kent Stalnaker

IPC: G11C11/24 ,  G11C11/4091 ,  G11C29/52 ,  G11C7/02 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/00 ,  G11C11/408 ,  G11C7/06

CPC classification number: G11C11/4091 ,  G11C7/00 ,  G11C7/02 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1069 ,  G11C7/1096 ,  G11C11/4087 ,  G11C11/4096 ,  G11C29/52

Abstract: A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.

Abstract translation: 一种存储数据的方法。 该方法包括提供包括存储器空间的可寻址存储器，其中存储器空间包括多个存储单元。 该方法包括配置可寻址存储器，使得当将一个或多个外部数据状态的第一外部数据状态写入存储器空间时，存储器空间中的多个存储器单元的大部分将内部数据值存储在优选偏置条件中， 其中所述第一外部数据状态与所述偏好条件相反。

公开(公告)号：US20150213847A1

公开(公告)日：2015-07-30

申请号：US14683687

申请日：2015-04-10

Applicant: Invensas Corporation

Inventor： David Edward Fisch ,  William C. Plants ,  Kent Stalnaker

IPC: G11C7/00

CPC classification number: G11C11/4091 ,  G11C7/00 ,  G11C7/02 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1069 ,  G11C7/1096 ,  G11C11/4087 ,  G11C11/4096 ,  G11C29/52

Abstract: A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.

Abstract translation: 一种存储数据的方法。 该方法包括提供包括存储器空间的可寻址存储器，其中存储器空间包括多个存储器单元。 该方法包括配置可寻址存储器，使得当将一个或多个外部数据状态的第一外部数据状态写入存储器空间时，存储器空间中的多个存储器单元的大部分将内部数据值存储在优选偏置条件中， 其中所述第一外部数据状态与优选偏置条件相反。