公开(公告)号：US20140264730A1

公开(公告)日：2014-09-18

申请号：US13800313

申请日：2013-03-13

Applicant: INVENSAS CORPORATION

Inventor： Belgacem Haba ,  David Fisch

IPC: H01L23/525 ,  H01L27/06

CPC classification number: H01L23/5256 ,  G11C5/02 ,  G11C7/10 ,  G11C7/20 ,  H01L24/06 ,  H01L24/16 ,  H01L27/06 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A semiconductor chip that may be configured to function as either a master chip or a slave chip. The semiconductor chip may be included in a microelectronic assembly including a plurality of vertically stacked semiconductor chips, with each of the chips containing functional circuit blocks that enable each semiconductor chip to function as either a master chip or a slave chip under in accordance with a state input stored on the same chip, or received from another chip in the stacked assembly or from another component of a system in which the stacked assembly is configured to operate.

Abstract translation: 可以被配置为用作主芯片或从芯片的半导体芯片。 半导体芯片可以包括在包括多个垂直堆叠的半导体芯片的微电子组件中，其中每个芯片包含功能电路块，其使得每个半导体芯片能够根据状态作为主芯片或从芯片 输入存储在同一芯片上，或者从堆叠组件中的另一个芯片或从堆叠组件配置为运行的系统的另一个组件接收。

公开(公告)号：US09153533B2

公开(公告)日：2015-10-06

申请号：US13800313

申请日：2013-03-13

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  David Fisch

IPC: G06F13/00 ,  G06F13/36 ,  G11C5/06 ,  H01L23/525 ,  H01L27/06 ,  G11C5/02 ,  G11C7/10 ,  G11C7/20 ,  H01L23/00

CPC classification number: H01L23/5256 ,  G11C5/02 ,  G11C7/10 ,  G11C7/20 ,  H01L24/06 ,  H01L24/16 ,  H01L27/06 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A semiconductor chip that may be configured to function as either a master chip or a slave chip. The semiconductor chip may be included in a microelectronic assembly including a plurality of vertically stacked semiconductor chips, with each of the chips containing functional circuit blocks that enable each semiconductor chip to function as either a master chip or a slave chip under in accordance with a state input stored on the same chip, or received from another chip in the stacked assembly or from another component of a system in which the stacked assembly is configured to operate.

Abstract translation: 可以被配置为用作主芯片或从芯片的半导体芯片。 半导体芯片可以包括在包括多个垂直堆叠的半导体芯片的微电子组件中，其中每个芯片包含功能电路块，其使得每个半导体芯片能够根据状态作为主芯片或从芯片 输入存储在同一芯片上，或者从堆叠组件中的另一个芯片或从堆叠组件配置为运行的系统的另一个组件接收。

公开(公告)号：US09705497B2

公开(公告)日：2017-07-11

申请号：US14829511

申请日：2015-08-18

Applicant: Invensas Corporation

Inventor： Curtis Dicke ,  George Courville ,  David Fisch ,  Randall Sandusky ,  Kent Stalnaker

IPC: H03L5/00 ,  H03K19/00 ,  H01C10/50 ,  G11C7/10 ,  H03F3/45

CPC classification number: H03K19/0005 ,  G11C7/1057 ,  H01C10/50 ,  H03F3/45475

Abstract: System and method for providing precision a self calibrating resistance circuit is described that provides for matching a reference resistor using dynamically configurable resistance networks. The resistor network is coupled to the connection, wherein the resistor network provides a configurable resistance across the connection. In addition, the resistor network comprises a digital resistor network and an analog resistor network. Also, the circuit includes control circuitry for configuring the configurable resistance based on a reference resistance of the reference resistor. The configurable resistance is configured by coarsely tuning the resistor network through the digital resistor network and fine tuning the resistor network through the analog resistor network.