Invention Grant
- Patent Title: Semiconductor device test apparatuses
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Application No.: US14495025Application Date: 2014-09-24
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Publication No.: US09733304B2Publication Date: 2017-08-15
- Inventor: Jaspreet S. Gandhi , Michel Koopmans , James M. Derderian
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G01R1/073

Abstract:
Apparatus for testing semiconductor devices comprising die stacks, the apparatus comprising a substrate having an array of pockets in a surface thereof arranged to correspond to conductive elements protruding from a semiconductor device to be tested. The pockets include conductive contacts with traces extending to conductive pads, which may be configured as test pads, jumper pads, edge connects or contact pads. The substrate may comprise a semiconductor wafer or wafer segment and, if the latter, multiple segments may be received in recesses in a fixture. Testing may be effected using a probe card, a bond head carrying conductive pins, or through conductors carried by the fixture.
Public/Granted literature
- US20160084905A1 APPARATUS FOR TESTING STACKED DIE ASSEMBLIES, AND RELATED METHODS Public/Granted day:2016-03-24
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