Invention Grant
- Patent Title: Low power threshold integrated micro-plasma limiter
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Application No.: US14708838Application Date: 2015-05-11
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Publication No.: US09774067B2Publication Date: 2017-09-26
- Inventor: Benjamin D. Poust , Michael Conrad Battung , Dino Ferizovic , Patty P. Chang-Chien
- Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION
- Applicant Address: US VA Falls Church
- Assignee: Northrop Grumman Systems Corporation
- Current Assignee: Northrop Grumman Systems Corporation
- Current Assignee Address: US VA Falls Church
- Agency: Miller IP Group, PLC
- Agent John A. Miller
- Main IPC: H01P1/14
- IPC: H01P1/14 ; H01T4/08 ; H01T4/16 ; H03G11/00 ; H01L23/60 ; H01T19/04

Abstract:
A plasma power limiter fabricated using wafer-level fabrication techniques with other circuit elements. The power limiter includes a signal substrate having a first side and a second side, an input signal line formed on the first side, a signal transmission line formed on the second side and an output signal line formed on the first side. The power limiter also includes a ground substrate having a first side and a second side, and being bonded to the signal substrate to form a sealed cavity including an ionizable gas therebetween. The ground substrate includes a ground metal layer formed on the second side. A signal propagating on the input signal line at a power level greater than a threshold power level generates a voltage potential across the cavity that ionizes the gas and generates a plasma discharge, and limits power of the output signal coupled to the output signal line.
Public/Granted literature
- US20150244048A1 LOW POWER THRESHOLD INTEGRATED MICRO-PLASMA LIMITER Public/Granted day:2015-08-27
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