公开(公告)号：US09484284B1

公开(公告)日：2016-11-01

申请号：US15072242

申请日：2016-03-16

Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION ,  GENERAL ELECTRIC COMPANY

Inventor： Vincent Gambin ,  Benjamin D. Poust ,  Dino Ferizovic ,  Stanton E. Weaver ,  Gary D. Mandrusiak

IPC: H01L33/32 ,  H01L29/20 ,  H01L21/02 ,  H01L23/473 ,  H01L29/205 ,  H01L29/778 ,  H01L23/367 ,  H01L23/373 ,  H01L27/095 ,  H01L23/66 ,  H03F3/213 ,  H03F3/193 ,  H03F3/195

CPC classification number: H01L23/4735 ,  H01L23/367 ,  H01L23/3732 ,  H01L23/66 ,  H01L27/095 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/778 ,  H01L2223/6644 ,  H01L2223/6683

Abstract: A MMIC power amplifier circuit assembly comprised of a SiC substrate having a plurality of microchannels formed therein, where a diamond layer is provided within each of the microchannels. A plurality of GaN HEMT devices are provided on the substrate where each HEMT device is positioned directly opposite to a microchannel. A silicon manifold is coupled to the substrate and includes a plurality of micro-machined channels formed therein that include a jet impingement channel positioned directly adjacent each microchannel, a return channel directly positioned adjacent to each microchannel, a supply channel supplying a cooling fluid to the impingement channels and a return channel collecting heated cooling fluid from the supply channels so that an impingement jet is directed on to the diamond layer for removing heat generated by the HEMT devices.

Abstract translation: 一种由在其中形成有多个微通道的SiC衬底组成的MMIC功率放大器电路组件，其中金属层设置在每个微通道内。 在基板上设置多个GaN HEMT器件，其中每个HEMT器件直接与微通道相对。 硅歧管联接到衬底并且包括形成在其中的多个微加工通道，其包括直接邻近每个微通道定位的喷射冲击通道，与每个微通道相邻直接定位的返回通道，向冷却流体供应冷却流体的供应通道 冲击通道和从供应通道收集加热的冷却流体的返回通道，使得冲击射流被引导到金刚石层以去除由HEMT装置产生的热量。

公开(公告)号：US09774067B2

公开(公告)日：2017-09-26

申请号：US14708838

申请日：2015-05-11

Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION

Inventor： Benjamin D. Poust ,  Michael Conrad Battung ,  Dino Ferizovic ,  Patty P. Chang-Chien

IPC: H01P1/14 ,  H01T4/08 ,  H01T4/16 ,  H03G11/00 ,  H01L23/60 ,  H01T19/04

CPC classification number: H01P1/14 ,  H01L23/60 ,  H01L2924/0002 ,  H01T4/08 ,  H01T4/16 ,  H01T19/04 ,  H03G11/002 ,  H03G11/004 ,  H01L2924/00

Abstract: A plasma power limiter fabricated using wafer-level fabrication techniques with other circuit elements. The power limiter includes a signal substrate having a first side and a second side, an input signal line formed on the first side, a signal transmission line formed on the second side and an output signal line formed on the first side. The power limiter also includes a ground substrate having a first side and a second side, and being bonded to the signal substrate to form a sealed cavity including an ionizable gas therebetween. The ground substrate includes a ground metal layer formed on the second side. A signal propagating on the input signal line at a power level greater than a threshold power level generates a voltage potential across the cavity that ionizes the gas and generates a plasma discharge, and limits power of the output signal coupled to the output signal line.