Invention Grant
- Patent Title: Customer-transparent logic redundancy for improved yield
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Application No.: US14995353Application Date: 2016-01-14
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Publication No.: US09791507B2Publication Date: 2017-10-17
- Inventor: Igor Arsovski , John R. Goss , Eric D. Hunt-Schroeder , Andrew K. Killorin
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Roberts Mlotkowski Safran Cole & Calderon, P.C.
- Agent Steven Meyers; Andrew M. Calderon
- Main IPC: G06F11/22
- IPC: G06F11/22 ; G06F17/50 ; G01R31/3177

Abstract:
Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.
Public/Granted literature
- US20160131706A1 CUSTOMER-TRANSPARENT LOGIC REDUNDANCY FOR IMPROVED YIELD Public/Granted day:2016-05-12
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