公开(公告)号：US10955474B2

公开(公告)日：2021-03-23

申请号：US16676776

申请日：2019-11-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor Arsovski ,  John R. Goss ,  Eric D. Hunt-Schroeder ,  Andrew K. Killorin

IPC: G06F30/3953 ,  G01R31/3177

Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.

公开(公告)号：US09274171B1

公开(公告)日：2016-03-01

申请号：US14539527

申请日：2014-11-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor Arsovski ,  John R. Goss ,  Eric D. Hunt-Schroeder ,  Andrew K. Killorin

IPC: G06F11/22 ,  G01R31/3177

CPC classification number: G01R31/3177

Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.

Abstract translation: 提供了系统和方法，用于在扫描链中实现客户透明的逻辑冗余，以提高集成电路的产量。 更具体地，提供了包括多个组合的锁存结构的集成电路结构。 组合的锁存结构中的每一个包括原始锁存器和冗余锁存器。 集成电路结构还包括多个组合的逻辑结构。 组合逻辑结构中的每一个包括原始逻辑结构冗余逻辑结构。 每个冗余锁存器是组合锁存结构内的每个相应的原始锁存器的副本，并且每个冗余逻辑结构是组合逻辑结构内每个相应的原始逻辑结构的重复，使得两个锁存器和逻辑库被提供给一个或 更多扫描链的集成电路结构。

公开(公告)号：US09224091B2

公开(公告)日：2015-12-29

申请号：US14202590

申请日：2014-03-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor Arsovski

IPC: G06N5/02 ,  G06N3/08 ,  G06N3/063

CPC classification number: G06N3/08 ,  G06N3/0445 ,  G06N3/049 ,  G06N3/063 ,  G06N5/02

Abstract: A circuit is provided for that includes one or more TCAM arrays including one or more matchlines configured to model a neural network. Each of the one or more TCAM arrays models a connected group of neurons such that input search data into the one or more matchlines is modeled as neuron dendrite information, and the output from the one or more matchlines is modeled as neuron axon information. The circuit further includes one or more additional bits included within each of the one or more matchlines that are configured to model connectivity strength between each neuron dendrite and axon. The circuit also includes a real-time learning block included within each of the one or more TCAM arrays configured to modify the connectivity strength between each neuron dendrite and axon using wild-cards written and stored in the one or more additional bits.

Abstract translation: 提供了一种电路，其包括一个或多个TCAM阵列，其包括被配置为对神经网络建模的一个或多个匹配线。 一个或多个TCAM阵列中的每一个模拟连接的神经元组，使得到一个或多个匹配线的输入搜索数据被建模为神经元树突信息，并且来自一个或多个匹配线的输出被建模为神经轴突信息。 该电路还包括一个或多个附加位，其包括在一个或多个匹配线中的每一个中，其被配置为模拟每个神经元树突与轴突之间的连接强度。 该电路还包括一个或多个TCAM阵列中的每一个中包括的实时学习块，其被配置为使用写入并存储在一个或多个附加位中的通配符来修改每个神经元枝晶与轴突之间的连接强度。

公开(公告)号：US09218880B2

公开(公告)日：2015-12-22

申请号：US14282298

申请日：2014-05-20

Applicant: International Business Machines Corporation

Inventor： Igor Arsovski ,  Derick G. Behrends ,  Todd A. Christensen ,  Travis R. Hebig ,  Michael Launsbach

IPC: G11C15/00 ,  G11C15/04 ,  G06F17/50

CPC classification number: G11C15/046 ,  G06F17/5054 ,  G06F2217/64 ,  G06F2217/86 ,  G11C15/04

Abstract: A TCAM may have a plurality of rows of cells. Each row may have a match line. Each cell may have elements for storing first and second bits, and compare circuitry associated to determine matches between a bit of a search word and data stored in the cell. For at least one first row of the rows, the TCAM includes a valid row cell having at least one element to store a partial update indication. The valid row cell may cause the match line associated with the first row to signal that the first row does not match a search word when the partial update indication associated with the first row is enabled. When the partial update indication associated with the first row is disabled, the determination of matches with a search word is performed solely by the compare circuitry without influence of the valid row cell.

Abstract translation: TCAM可以具有多行单元。 每行可能有一个匹配行。 每个小区可以具有用于存储第一和第二比特的元素，并且比较相关联的电路以确定搜索词的比特和存储在小区中的数据之间的匹配。 对于行的至少一行第一行，TCAM包括具有至少一个元素以存储部分更新指示的有效行单元。 当与第一行相关联的部分更新指示被启用时，有效行单元可能导致与第一行相关联的匹配行表示第一行与搜索词不匹配。 当与第一行相关联的部分更新指示被禁用时，与搜索字匹配的确定仅由比较电路执行而不影响有效行单元。

公开(公告)号：US09177646B2

公开(公告)日：2015-11-03

申请号：US13888108

申请日：2013-05-06

Applicant: International Business Machines Corporation

Inventor： Igor Arsovski

IPC: G11C15/00 ,  G11C15/04 ,  G06F17/30 ,  G11C11/56 ,  G06F11/10 ,  G06F12/10

CPC classification number: G11C15/04 ,  G06F11/1064 ,  G06F12/1027 ,  G06F17/30982 ,  G11C11/5642 ,  G11C15/043

Abstract: A content-addressable memory (CAM) with computational capability is described. The CAM includes an array of CAM cells arranged in rows and columns with a pair of search lines associated with each column of the array and a match line associated with each row of the array. The array of CAM cells is configured to implement, for a given cycle, either a read operation of data contained in a single selected column, or one of a plurality of different bitwise logical operations on data contained in multiple selected columns. All of the pairs of search lines in the columns of the array are configured to a certain state to implement the read operation or one of the plurality of different bitwise logical operations. A result of the read operation or one of the plurality of different bitwise logical operations is outputted onto all of the match lines in the array.

Abstract translation: 描述了具有计算能力的内容寻址存储器（CAM）。 CAM包括以行和列布置的一系列CAM单元阵列，其中具有与阵列的每列相关联的一对搜索线以及与阵列的每一行相关联的匹配线。 CAM单元的阵列被配置为针对给定的周期对包含在单个选定的列中的数据的读取操作或对包含在多个选定的列中的数据的多个不同的按位逻辑运算中的一个执行。 阵列列中的所有搜索线对被配置为一定的状态以实现读取操作或多个不同的逐位逻辑运算中的一个。 将读取操作或多个不同的按位逻辑运算中的一个输出到阵列中的所有匹配线上。

公开(公告)号：US09172371B2

公开(公告)日：2015-10-27

申请号：US13948567

申请日：2013-07-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor Arsovski ,  Robert M. Houle

IPC: G11C5/14 ,  H03K19/00 ,  H01L25/00 ,  H03K19/003 ,  G11C11/419

CPC classification number: H03K19/003 ,  G11C11/419

Abstract: Methods and structures for configuring an integrated circuit including repeated cells that are divided into banks having a respective power assist and a respective operational assist are provided. A method includes configuring the banks without power assist and operational assist. The method further includes selecting the power assist for a bank based on a determination that a weak cell remains in the bank after configuring the bank with the respective operational assist.

Abstract translation: 提供了用于配置集成电路的方法和结构，所述集成电路包括被划分为具有相应的电力辅助的行的重复单元和相应的操作辅助。 一种方法包括配置银行而无需电力辅助和操作辅助。 该方法还包括基于在用相应的操作辅助配置银行之后，确定弱电池保留在银行中的银行的电力辅助。

公开(公告)号：US09171125B2

公开(公告)日：2015-10-27

申请号：US14190723

申请日：2014-02-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor Arsovski ,  Jeanne P. Bickford ,  Mark W. Kuemerle

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F2217/78 ,  G06F2217/84

Abstract: Methods and systems are provided for that are designed to impose an n-type to p-type device skew constraint that is beyond what normal technology limits allow in order to operate semiconductor devices at lower voltages while still achieving a similar performance at a lower power. More specifically, a method is provided for that includes setting device skew requirements for at least one library element, setting device skew test dispositions for the at least one library element based on the set device skew requirements, designing the at least one library element using device skew assumptions, fabricating the at least one library element on a product that includes at least one device skew monitor, determining an actual device skew of the fabricated at least one library element using the at least one device skew monitor, and determining whether the fabricated product meets target specifications.

Abstract translation: 提供的方法和系统被设计为施加n型到p型装置偏斜约束，该约束超出正常技术限制允许以在较低电压下操作半导体器件，同时仍然在较低功率下实现类似的性能。 更具体地，提供了一种方法，其包括：针对至少一个库元素设置设备偏斜要求，基于设置的设备偏差要求来设置用于至少一个库元素的设备偏斜测试配置，使用设备来设计至少一个库元素 在产品上制造包括至少一个设备偏斜监视器的至少一个库元件，使用至少一个设备偏斜监视器确定所制造的至少一个库元件的实际设备偏差，以及确定所制造的产品 达到目标规格。

公开(公告)号：US10204685B2

公开(公告)日：2019-02-12

申请号：US14818764

申请日：2015-08-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor Arsovski ,  Suparna Bhattacharya ,  Arvind Kumar

IPC: G06F12/00 ,  G11C15/04 ,  G06F12/14

Abstract: Ternary content addressable memory (TCAM) structures and methods of use are disclosed. The memory architecture includes one or more ternary content addressable memory (TCAM) fields, and control logic that applies progressively discriminating data-masking and scores a closeness of a match based on matched and mismatched bits.

公开(公告)号：US09791507B2

公开(公告)日：2017-10-17

申请号：US14995353

申请日：2016-01-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor Arsovski ,  John R. Goss ,  Eric D. Hunt-Schroeder ,  Andrew K. Killorin

IPC: G06F11/22 ,  G06F17/50 ,  G01R31/3177

CPC classification number: G01R31/3177

Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.

公开(公告)号：US20160313394A1

公开(公告)日：2016-10-27

申请号：US14695112

申请日：2015-04-24

Applicant: International Business Machines Corporation

Inventor： Igor Arsovski ,  Jeanne P. Bickford ,  Paul J. Grzymkowski ,  Susan K. Lichtensteiger ,  Robert J. McMahon ,  Troy J. Perry ,  David M. Picozzi ,  Thomas G. Sopchak

IPC: G01R31/28 ,  H01L21/67

CPC classification number: G01R31/2894 ,  G01R21/133 ,  G01R31/31718 ,  G06F17/5045 ,  G06F2217/78

Abstract: Disclosed is a method wherein selective voltage binning and leakage power screening of integrated circuit (IC) chips are performed. Additionally, pre-test power-optimized bin reassignments are made on a chip-by-chip basis. Specifically, a leakage power measurement of an IC chip selected from a voltage bin can is compared to a bin-specific leakage power screen value of the next slower voltage bin. If the leakage power measurement is higher, the IC chip will be left in the voltage bin to which it is currently assigned. If the leakage power measurement is lower, the IC chip will be reassigned to that next slower voltage bin. These processes can be iteratively repeated until no slower voltage bins are available or the IC chip cannot be reassigned. IC chips can subsequently be tested according to testing parameters, including the minimum test voltages, associated with the voltage bins to which they are finally assigned.

Abstract translation: 公开了一种其中执行集成电路（IC）芯片的选择性电压组合和漏电功率筛选的方法。 另外，预先测试功率优化的bin重新分配是在逐个芯片的基础上进行的。 具体地，将从电压仓罐选择的IC芯片的泄漏功率测量值与下一个较慢电压箱的二进制特定泄漏功率屏幕值进行比较。 如果泄漏功率测量值较高，则IC芯片将保留在当前分配给它的电压仓中。 如果泄漏功率测量值较低，则IC芯片将重新分配给下一个较慢的电压仓。 这些过程可以迭代重复，直到没有较慢的电压箱可用或IC芯片不能重新分配。 IC芯片随后可以根据测试参数进行测试，包括与最终分配给它们的电压箱相关联的最小测试电压。