公开(公告)号：US11293980B2

公开(公告)日：2022-04-05

申请号：US17132820

申请日：2020-12-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor Arsovski ,  John R. Goss ,  Eric D. Hunt-Schroeder ,  Andrew K. Killorin

IPC: G01R31/3177

Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.

公开(公告)号：US10551436B2

公开(公告)日：2020-02-04

申请号：US15700597

申请日：2017-09-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor Arsovski ,  John R. Goss ,  Eric D. Hunt-Schroeder ,  Andrew K. Killorin

IPC: G01R31/3177

Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.

公开(公告)号：US10955474B2

公开(公告)日：2021-03-23

申请号：US16676776

申请日：2019-11-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor Arsovski ,  John R. Goss ,  Eric D. Hunt-Schroeder ,  Andrew K. Killorin

IPC: G06F30/3953 ,  G01R31/3177

Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.

公开(公告)号：US09779783B2

公开(公告)日：2017-10-03

申请号：US14744800

申请日：2015-06-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Darren L. Anand ,  John A. Fifield ,  Eric D. Hunt-Schroeder ,  Mark D. Jacunski

IPC: G11C7/06 ,  G11C17/18

CPC classification number: G11C7/065 ,  G11C17/18 ,  G11C2207/063

Abstract: A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.

公开(公告)号：US09274171B1

公开(公告)日：2016-03-01

申请号：US14539527

申请日：2014-11-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor Arsovski ,  John R. Goss ,  Eric D. Hunt-Schroeder ,  Andrew K. Killorin

IPC: G06F11/22 ,  G01R31/3177

CPC classification number: G01R31/3177

Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.

Abstract translation: 提供了系统和方法，用于在扫描链中实现客户透明的逻辑冗余，以提高集成电路的产量。 更具体地，提供了包括多个组合的锁存结构的集成电路结构。 组合的锁存结构中的每一个包括原始锁存器和冗余锁存器。 集成电路结构还包括多个组合的逻辑结构。 组合逻辑结构中的每一个包括原始逻辑结构冗余逻辑结构。 每个冗余锁存器是组合锁存结构内的每个相应的原始锁存器的副本，并且每个冗余逻辑结构是组合逻辑结构内每个相应的原始逻辑结构的重复，使得两个锁存器和逻辑库被提供给一个或 更多扫描链的集成电路结构。

公开(公告)号：US09791507B2

公开(公告)日：2017-10-17

申请号：US14995353

申请日：2016-01-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Igor Arsovski ,  John R. Goss ,  Eric D. Hunt-Schroeder ,  Andrew K. Killorin

IPC: G06F11/22 ,  G06F17/50 ,  G01R31/3177

CPC classification number: G01R31/3177

Abstract: Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.