- Patent Title: Heuristics for improving performance in a tile based architecture
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Application No.: US14046856Application Date: 2013-10-04
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Publication No.: US09792122B2Publication Date: 2017-10-17
- Inventor: Ziyad S. Hakura , Walter R. Steiner , Cynthia Ann Edgeworth Allison , Rouslan Dimitrov , Karim M. Abdalla , Dale L. Kirkland , Emmett M. Kilgariff
- Applicant: NVIDIA CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA CORPORATION
- Current Assignee: NVIDIA CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Artegis Law Group, LLP
- Main IPC: G06F9/38
- IPC: G06F9/38 ; G06T15/80 ; G06F9/44 ; G06F12/08 ; G06T15/50 ; G09G5/395 ; G09G5/00 ; G06T15/40 ; G06T1/20 ; G06T1/60 ; G06T15/00 ; G06F12/0808 ; G06F12/0875

Abstract:
One embodiment of the present invention includes a technique for processing graphics primitives in a tile-based architecture. The technique includes storing, in a buffer, a first plurality of graphics primitives and a first plurality of state bundles received from the world-space pipeline. The technique further includes determining, based on a first condition, that the first plurality of graphics primitives should be replayed from the buffer, and, in response, replaying the first plurality of graphics primitives against a first tile included in a first plurality of tiles. Replaying the first plurality of graphics primitives includes comparing each graphics primitive against the first tile to determine whether the graphics primitive intersects the first tile, determining that one or more graphics primitives intersects the first tile, and transmitting the one or more graphics primitives and one or more associated state bundles to a screen-space pipeline for processing.
Public/Granted literature
- US20140118376A1 HEURISTICS FOR IMPROVING PERFORMANCE IN A TILE BASED ARCHITECTURE Public/Granted day:2014-05-01
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