公开(公告)号：US09792122B2

公开(公告)日：2017-10-17

申请号：US14046856

申请日：2013-10-04

Applicant: NVIDIA CORPORATION

Inventor： Ziyad S. Hakura ,  Walter R. Steiner ,  Cynthia Ann Edgeworth Allison ,  Rouslan Dimitrov ,  Karim M. Abdalla ,  Dale L. Kirkland ,  Emmett M. Kilgariff

IPC: G06F9/38 ,  G06T15/80 ,  G06F9/44 ,  G06F12/08 ,  G06T15/50 ,  G09G5/395 ,  G09G5/00 ,  G06T15/40 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00 ,  G06F12/0808 ,  G06F12/0875

CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

Abstract: One embodiment of the present invention includes a technique for processing graphics primitives in a tile-based architecture. The technique includes storing, in a buffer, a first plurality of graphics primitives and a first plurality of state bundles received from the world-space pipeline. The technique further includes determining, based on a first condition, that the first plurality of graphics primitives should be replayed from the buffer, and, in response, replaying the first plurality of graphics primitives against a first tile included in a first plurality of tiles. Replaying the first plurality of graphics primitives includes comparing each graphics primitive against the first tile to determine whether the graphics primitive intersects the first tile, determining that one or more graphics primitives intersects the first tile, and transmitting the one or more graphics primitives and one or more associated state bundles to a screen-space pipeline for processing.

公开(公告)号：US09639366B2

公开(公告)日：2017-05-02

申请号：US14045372

申请日：2013-10-03

Applicant: NVIDIA CORPORATION

Inventor： Karim M. Abdalla ,  Ziyad S. Hakura ,  Cynthia Ann Edgeworth Allison ,  Dale L. Kirkland

IPC: G09G5/36 ,  G06F9/38 ,  G06T15/00 ,  G06T15/40 ,  G06T1/20 ,  G06T1/60 ,  G09G5/395 ,  G09G5/00 ,  G06T15/50 ,  G06F12/0808 ,  G06F12/0875 ,  G06F9/44 ,  G06T15/80

CPC classification number: G06T1/20 ,  G06F9/38 ,  G06F9/44 ,  G06F12/0808 ,  G06F12/0875 ,  G06F2212/302 ,  G06T1/60 ,  G06T15/005 ,  G06T15/405 ,  G06T15/503 ,  G06T15/80 ,  G06T17/20 ,  G09G5/003 ,  G09G5/395 ,  Y02D10/13

Abstract: One embodiment of the present invention sets forth a technique for managing buffer table entries in a tile-based architecture. The technique includes binding a plurality of shader registers to a buffer table entry. The technique further includes processing at least one tile by reading a buffer table index stored in the shader register to access the buffer table entry, reading a buffer address stored in the buffer table entry, accessing data associated with the buffer address, and unbinding the shader register from the buffer table entry. The technique further includes determining that none of the shader registers is still bound to the buffer table entry and, in response, causing a release packet to be inserted into an instruction stream. The technique further includes determining that a last tile has been processed and, in response, transmitting the release packet to cause the buffer table entry to be released.