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公开(公告)号：US09792122B2
公开(公告)日：2017-10-17
申请号：US14046856
申请日：2013-10-04
Applicant: NVIDIA CORPORATION
Inventor： Ziyad S. Hakura , Walter R. Steiner , Cynthia Ann Edgeworth Allison , Rouslan Dimitrov , Karim M. Abdalla , Dale L. Kirkland , Emmett M. Kilgariff
IPC: G06F9/38 , G06T15/80 , G06F9/44 , G06F12/08 , G06T15/50 , G09G5/395 , G09G5/00 , G06T15/40 , G06T1/20 , G06T1/60 , G06T15/00 , G06F12/0808 , G06F12/0875
CPC classification number: G06T1/20 , G06F9/38 , G06F9/44 , G06F12/0808 , G06F12/0875 , G06F2212/302 , G06T1/60 , G06T15/005 , G06T15/405 , G06T15/503 , G06T15/80 , G06T17/20 , G09G5/003 , G09G5/395 , Y02D10/13
Abstract: One embodiment of the present invention includes a technique for processing graphics primitives in a tile-based architecture. The technique includes storing, in a buffer, a first plurality of graphics primitives and a first plurality of state bundles received from the world-space pipeline. The technique further includes determining, based on a first condition, that the first plurality of graphics primitives should be replayed from the buffer, and, in response, replaying the first plurality of graphics primitives against a first tile included in a first plurality of tiles. Replaying the first plurality of graphics primitives includes comparing each graphics primitive against the first tile to determine whether the graphics primitive intersects the first tile, determining that one or more graphics primitives intersects the first tile, and transmitting the one or more graphics primitives and one or more associated state bundles to a screen-space pipeline for processing.
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Patent Agency Ranking
公开(公告)号：US10282803B2
公开(公告)日：2019-05-07
申请号：US14016789
申请日：2013-09-03
Applicant: NVIDIA CORPORATION
Inventor： Ziyad S. Hakura , Pierre Souillot , Cynthia Ann Edgeworth Allison , Dale L. Kirkland , Walter R. Steiner
IPC: G09G5/36 , G06T1/20 , G06T15/00 , G06T15/40 , G06F9/38 , G06T1/60 , G09G5/395 , G09G5/00 , G06T15/50 , G06F12/0808 , G06F12/0875 , G06F9/44 , G06T15/80 , G06T17/20
Abstract: One embodiment of the present invention includes a graphics subsystem that includes a tiling unit, a crossbar unit, and a screen-space pipeline. The crossbar unit is configured to transmit primitives interleaved with state change commands to the tiling unit. The tiling unit is configured to record an initial state associated with the primitives and to transmit to the screen-space pipeline one or more primitives in the primitives that overlap a first cache tile. The tiling unit is further configured to transmit the initial state to the screen-space pipeline and to transmit to the screen-space pipeline one or more primitives in the primitives that overlap a second cache tile. The tiling unit includes a state filter block configured to determine that a first state change in the state change commands is followed by a second state change, without an intervening primitive, and to forego transmitting the first state change in response.
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公开(公告)号：US09947084B2
公开(公告)日：2018-04-17
申请号：US13790037
申请日：2013-03-08
Applicant: NVIDIA Corporation
Inventor： Eric B. Lum , John S. Montrym , Walter R. Steiner , Justin Cobb , Henry Packard Moreton
CPC classification number: G06T5/006 , G06T15/005
Abstract: A technique for multiresolution consistent rasterization in which a setup unit calculates universal edge equations for a universal resolution. A rasterizer evaluates coverage data for two different resolutions based on the edge equations. The rasterizer evaluates coverage data for different effective pixel sizes—a large pixel size and a small pixel size. Optionally, the rasterizer may determine a first set of coverage data by performing conservative rasterization to determine coverage data for large pixels. Optionally, the rasterizer may then determine a second set of coverage data by performing standard rasterization for small pixels. Optionally, for the second set of coverage data, the rasterizer may evaluate only the small pixels that are within large pixels in the first set of coverage data that evaluate as covered.
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公开(公告)号：US09311733B2
公开(公告)日：2016-04-12
申请号：US13828752
申请日：2013-03-14
Applicant: NVIDIA CORPORATION
Inventor： Walter R. Steiner , Eric B. Lum
CPC classification number: G06T11/40
Abstract: One embodiment of the present invention sets forth a technique for improved rasterization of round points mapped into a tile space within a graphics processing pipeline. A set of candidate tiles are selected based on proximity to a round point. A tile within the set of candidate tiles may be rejected based on a rejection boundary. A tile may be rejected if no vertex associated with the tile is within the coverage area. Performance is improved by rejecting certain unneeded tiles that would otherwise be included in conventional rasterization. One embodiment advantageously enlists line drawing circuitry to determine whether a given tile intersects the coverage area.
Abstract translation: 本发明的一个实施例提出了一种用于改进映射到图形处理流水线内的瓦片空间的圆点的光栅化的技术。 基于与圆点的接近度来选择一组候选瓦片。 候选瓦片组内的瓦片可以基于拒绝边界被拒绝。 如果与瓦片相关联的顶点不在覆盖区域内，则瓦片可能被拒绝。 通过拒绝否则将包括在常规光栅化中的某些不需要的瓦片来改善性能。 一个实施例有利地引入线绘图电路以确定给定的瓦片是否与覆盖区域相交。
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公开(公告)号：US10032243B2
公开(公告)日：2018-07-24
申请号：US14058053
申请日：2013-10-18
Applicant: NVIDIA Corporation
Abstract: One embodiment of the present invention sets forth a graphics subsystem configured to implement distributed cache tiling. The graphics subsystem includes one or more world-space pipelines, one or more screen-space pipelines, one or more tiling units, and a crossbar unit. Each world-space pipeline is implemented in a different processing entity and is coupled to a different tiling unit. Each screen-space pipeline is implemented in a different processing entity and is coupled to the crossbar unit. The tiling units are configured to receive primitives from the world-space pipelines, generate cache tile batches based on the primitives, and transmit the primitives to the screen-space pipelines. One advantage of the disclosed approach is that primitives are processed in application-programming-interface order in a highly parallel tiling architecture. Another advantage is that primitives are processed in cache tile order, which reduces memory bandwidth consumption and improves cache memory utilization.
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公开(公告)号：US09483270B2
公开(公告)日：2016-11-01
申请号：US14058145
申请日：2013-10-18
Applicant: NVIDIA Corporation
IPC: G06F9/38 , G06T15/00 , G06T15/40 , G06T1/20 , G06T1/60 , G09G5/395 , G09G5/00 , G06T15/50 , G06F12/08 , G06F9/44 , G06T15/80
CPC classification number: G06T1/20 , G06F9/38 , G06F9/44 , G06F12/0808 , G06F12/0875 , G06F2212/302 , G06T1/60 , G06T15/005 , G06T15/405 , G06T15/503 , G06T15/80 , G06T17/20 , G09G5/003 , G09G5/395 , Y02D10/13
Abstract: One embodiment of the present invention sets forth a graphics subsystem configured to implement distributed tiled caching. The graphics subsystem includes one or more world-space pipelines, one or more screen-space pipelines, one or more tiling units, and a crossbar unit. Each world-space pipeline is implemented in a different processing entity and is coupled to a different tiling unit. Each screen-space pipeline is implemented in a different processing entity and is coupled to the crossbar unit. The tiling units are configured to receive primitives from the world-space pipelines, generate cache tile batches based on the primitives, and transmit the primitives to the screen-space pipelines. One advantage of the disclosed approach is that primitives are processed in application-programming-interface order in a highly parallel tiling architecture. Another advantage is that primitives are processed in cache tile order, which reduces memory bandwidth consumption and improves cache memory utilization.
Abstract translation: 本发明的一个实施例提出了一种被配置为实现分布式平铺高速缓存的图形子系统。 图形子系统包括一个或多个世界空间管道，一个或多个屏幕空间管道，一个或多个平铺单元和横梁单元。 每个世界空间流水线在不同的处理实体中实现，并且耦合到不同的平铺单元。 每个屏幕空间流水线在不同的处理实体中实现，并且耦合到交叉开关单元。 拼接单元被配置为从世界空间管道接收原语，基于图元生成高速缓存块批次，并将基元发送到屏幕空间管道。 所公开的方法的一个优点是在高度并行的平铺架构中以应用编程接口顺序处理原语。 另一个优点是以缓存平铺顺序处理图元，从而减少内存带宽消耗并提高高速缓存的使用率。
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