- Patent Title: Interconnect integration for sidewall pore seal and via cleanliness
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Application No.: US14750778Application Date: 2015-06-25
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Publication No.: US09793108B2Publication Date: 2017-10-17
- Inventor: He Ren , Mehul B. Naik , Deenesh Padhi , Priyanka Dash , Bhaskar Kumar , Alexandros T. Demos
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: APPLIED MATERIAL, INC.
- Current Assignee: APPLIED MATERIAL, INC.
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson + Sheridan LLP
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L21/31 ; C23C16/36 ; H01L21/3105 ; C23C16/04 ; C23C16/48 ; C23C16/56

Abstract:
A method for sealing porous low-k dielectric films is provided. The method comprises exposing a substrate to UV radiation and a first reactive gas, wherein the substrate has an open feature defined therein, the open feature defined by a porous low-k dielectric layer and a conductive material, wherein the porous low-k dielectric layer is a silicon and carbon containing material and selectively forming a pore sealing layer in the open feature on exposed surfaces of the porous low-k dielectric layer using UV assisted photochemical vapor deposition.
Public/Granted literature
- US20160379819A1 INTERCONNECT INTEGRATION FOR SIDEWALL PORE SEAL AND VIA CLEANLINESS Public/Granted day:2016-12-29
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