- 专利标题: Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects
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申请号: US14912036申请日: 2013-09-27
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公开(公告)号: US09793163B2公开(公告)日: 2017-10-17
- 发明人: Robert L. Bristol , Florian Gstrein , Richard E. Schenker , Paul A. Nyhus , Charles H. Wallace , Hui Jae Yoo
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Schwabe, Williamson & Wyatt P.C.
- 国际申请: PCT/US2013/062319 WO 20130927
- 国际公布: WO2015/047318 WO 20150402
- 主分类号: H01L21/768
- IPC分类号: H01L21/768 ; H01L21/311 ; H01L23/522 ; H01L23/528
摘要:
Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The interconnect structure further includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. The metal lines of the first grating are spaced apart from the metal lines of the second grating.
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